Abstract: A combination of one or more shift registers with a binary counter and a memory device is disclosed wherein binary information inputs are supplied to the shift register through a plurality of AND gates which also receive inputs from a pulse generator and the output of the shift register is supplied through a second plurality of AND gates to a storage device, and wherein the binary counter supplies inputs to the second plurality of AND gates, and wherein the pulse generator supplies outputs to the shift register, the binary counter and to the first plurality of AND gates. A second embodiment provides a plurality of shift registers which receive outputs from the first shift register and are connected to a plurality of memories through additional AND gates which are controlled by the pulse generator and the associated shift register.

Abstract: An electronic counter is provided for electrical digital pulses including a counter chain comprising idential flip-flop cells to be controlled by way of a counting input by means of pulses to be counted. By means of each counting pulse given to the counting input, at least one change of the operating state of the first flip-flop cell occurs into the respectively other operating state and in which, in addition, upon a second change of the operating state of the individual flip-flop cells of the counter chain, a simultaneous change of the operating state of at least one flip-flop cell, subsequently connected to the flip-flop cell concerned or, respectively, a resetting of the operating states of all flip-flop cells of the counter chain is provided into an initial state corresponding to the counter reading ZERO.

Abstract: Reset pulses are to be generated independently of a general reset system provided in a digital circuit to be operated by closing a switch and serve for resetting primarily only one portion of the digital system to be driven, so that that portion is reset into the initial digital condition, whereas the remaining portion of the system continues to cycle unfluenced by such reset pulses. In one embodiment a quasi-stationary shift register cell operates to provide the reset pulses in conjunction with an output gate and in another embodiment a modified master-slave flip-flop cell provides the reset pulses, also in conjunction with an output gate.

Abstract: A device for producing two clock pulse trains from a periodic signal comprised of waveforms of any shape produces digital pulses having the same period and further having respective duty cycles which are separated by pauses when the pulse series are aligned. The device consists two flip flop cells and two push-pull transistor outputs respectively connected thereto, each push-pull output having an output tap between the transistors. One flip flop cell is connected directly to a waveform source, and the other flip flop cell is connected to the waveform source via a transistor follower circuit.

Abstract: An information transmission system for N information signals for the transmission of either N parallel signals, or of only one information signal from a signal range of M signals with M.ltoreq.N at the upper or lower range boundary. N signal transmission gates are provided which can selectively be switched effective, these gates being connected through by means of control signals either for N information signals or for the signals at the upper or lower boundary of a signal range.