Abstract: A digital semiconductor circuit has at least two circuit parts, each including a counting chain having identical memory cells which serve for receiving and transmitting digital information. The counters are controlled by a common clock. The counter of the first circuit part is coupled to a signal generator which emits a digital pulse upon reading a predetermined, specific digital state of the counter of the first part. The signal generator emits a digital pulse which is superposed on a clock pulse so as to amplitude modulate the same. The modulated clock pulse is detected by a signal recognition circuit of the second circuit part to trigger a correction signal generator which sets the counter of the second circuit part to a predetermined count.