Abstract: A communication system includes a data exchange interface which is coupled via an internal bus to a microprocessor and a DMA unit. For controlling the data exchange, the interface transmits control signals either to a microprocessor or a DMA unit. The control signals are acknowledged each time. For realizing an efficient data exchange via the interface, the interface is an I.sup.2 C bus interface with minimum load of the microprocessor, and transmits a first group of control signals by a first control line to the DMA unit and a second group of control signals by a second control line to the microprocessor. By respective settings of the interface, a selectable part of the control circuitry may be transferred from the microprocessor to the DMA unit. The total number and type of control signals (interrupts) which correspond each to a specific mode of the interface may be retained.

Abstract: The invention discloses a communication system for exchanging data between a bus and at least one coupled data processing arrangement via a serial interface which is coupled to a microprocessor by a control line via a DMA unit. For effecting an efficient data exchange between a bus and a serial interface by means of a DMA unit while the controlling microprocessor is slightly loaded, the DMA unit, while in an active state featuring an interrupt mode, is provided for transferring an interface control signal to the microprocessor by the control line and, while in an inactive state featuring a DMA mode, is provided for forming at least one DMA control signal from the interface control signal and for transferring the formed DMA control signals to the microprocessor by the control line. For utilizing a serial interface for a data exchange both in the interrupt mode and in the DMA mode, the control line is looped through by the DMA unit.

Abstract: A circuit arrangement for storing a speech signal in a digital speech memory (SP) and reproducing the stored signal comprises among other things a control circuit (SS). The control circuit produces control commands and clock signals for the individual modules of the arrangement. The speech signal to be stored is available in one of various predetermined codes. In order to enable storing speech signals of considerable lengths, it is provided to write the speech signal into the digital speech memory (SS) in a preferred digital code. For this purpose, input converters (EW1, EW2, EW3, EW4) are used which convert the code of the speech signal to be stored from the one it has into the preferred digital code, if the signal is not already available in this code. Multiplexing means (M1, M2), controlled by the control circuit (SS), further convey the converted speech signal to the input of the digital speech memory (SP).