Abstract: Communication control functions are performed by an integrated adapter implemented as microcode resident in host CPU storage. The integrated adapter shares a common high speed bus with other CPU facilities. A high speed bus adapter provides an interface between the common high speed bus and low speed line adapters. Communication controlling commands and register structures are described.

Abstract: An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Instructions from the different programs are executed during different successive time slice intervals. The instruction execution modification mechanism is responsive to the occurrences of various predetermined conditions in the data processing system for selectively modifying the normal execution of different ones of the instructions in different ones of the programs. To this end, there is provided a program list mechanism listing the modifiable programs, an instruction list mechanism listing the modifiable instructions and a modification storage mechanism for storing modification signals for the different instructions.