Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region and along the sidewalls of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

Abstract: A field effect transistor includes two channel connection regions, a control region with at least two control sections, an active region that is formed as a projection of a mono crystalline substrate disposed between the channel connection regions and between two control region sections, and insulating regions that are electrically insulating and are disposed between the control region sections and the active region. The projection is isolated from the substrate at a base by an insulating material that is electrically insulating. The insulating material ends laterally at the projection in the mono crystalline substrate.

Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

Abstract: A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

Abstract: One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.

Abstract: A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

Abstract: The invention relates to a method for producing a capacitor arrangement, and to a corresponding capacitor arrangement, wherein the first insulating layer is formed at the surface of a carrier substrate and a first capacitor electrode with a multiplicity of interspaced first interconnects is produced in said insulating layer. Using a mask layer, partial regions of the first insulating layer are removed for the purpose of uncovering the multiplicity of first interconnects, and after the formation of a capacitor dielectric at the surface of the uncovered first interconnects, a second capacitor electrode is formed with a multiplicity of interspaced second interconnects lying between the first interconnects coated with capacitor dielectric. This additionally simplified production method enables self-aligning and cost-effective production of capacitors having a high capacitance per unit area and mechanical stability.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.

Abstract: A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.

Abstract: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip; a conductive layer comprising at least a first conductive pathway and a second conductive pathway spacedly disposed from the first conductive pathway, the first conductive pathway electrically coupled to the chip, at least a portion of the first conductive pathway disposed outside the lateral boundary of the chip, at least a portion of the second conductive pathway disposed outside the lateral boundary of the chip; and a conductive interconnect disposed outside the lateral boundary of the chip, the conductive interconnect electrically coupling the first conductive pathway to the second conductive pathway.

Abstract: A vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.

Abstract: One or more embodiments are related to a semiconductor structure, comprising: a semiconductor chip having a final metal layer; a dielectric layer disposed over the final metal layer; and a conductive layer deposed over the dielectric layer, the dielectric layer being between the final metal layer and the conductive layer.

Abstract: A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material.

Abstract: A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.

Abstract: A method for producing a field effect transistor, in which a plurality of layers are in each case deposited, planarized and etched back, in particular a gate electrode layer, is disclosed. This method allows the manufacturing of transistors having outstanding electrical properties and having outstanding reproducibility.