Abstract: An incoming a-c signal, whose amplitude is to be measured, successively passes through several decadic attenuator stages settable by respective cascaded decadic stages of a reversible counter. The attenuated signal is rectified and its voltage, or the RMS value thereof obtained from a squarer, gives rise to a calibration current, opposed by a constant reference current, for charging a capacitor of a current/frequency converter with a resulting current corresponding to their difference. Two threshold detectors in that converter, responding to a capacitor charge of either polarity beyond a predetermined limit, trigger a monoflop which fully or partly discharges the capacitor and steps the counter forward or backward as determined by a polarity sensor connected across the capacitor. A retriggerable second monoflop, responsive to the trailing edge of each stepping pulse, enables the second-lowest counter stage to be stepped out of turn when these pulses follow one another at high rate.