Patents by Inventor Helmut Wurzer

Helmut Wurzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7465522
    Abstract: A photolithographic mask having half tone main features and perpendicular half tone assist features. One embodiment provides for the exposure of radiation-sensitive resist layers on semiconductor substrates. The mask has at least one radiation-transmissive substrate and at least one half-tone layer. The half-tone layer is used to provide main features, the main features being formed in such a way that the pattern formed by the main features is transferred into the resist layer when irradiated, and the half-tone layer is also used to provide assist features, the assist features being formed substantially perpendicular to the main features in such a way that the pattern formed by the assist features is not transferred into the resist layer when irradiated.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: December 16, 2008
    Assignee: Infineon Technologies AG
    Inventors: Lothar Bauch, Gerhard Kunkel, Hermann Sachse, Helmut Wurzer
  • Patent number: 7078133
    Abstract: A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose pattern is not imaged into the resist layer, makes it possible to achieve a significant improvement in the imaging properties of the main structures which are disposed at an edge of a region containing a multiplicity of main structures. In particular, constrictions at the structures can be significantly reduced or completely avoided and/or a so-called “tilting” of the structures under non-optimum focus conditions is significantly reduced or completely avoided.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: July 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Lothar Bauch, Robert Feurle, Ina Voigt, Helmut Wurzer
  • Patent number: 6960541
    Abstract: A semiconductor element with at least one layer of tungsten oxide, optionally in a structured tungsten oxide layer, is described. The semiconductor element is characterized in that the relative premittivity of the tungsten oxide layer is higher than 50.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: November 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Dirk Drescher, Helmut Tews, Martin Schrems, Helmut Wurzer
  • Patent number: 6958282
    Abstract: A semiconductor configuration has a base layer made of semiconductor material and formed, in particular, by a substrate. An insulation layer is arranged above the base layer, and a layer made of monocrystalline silicon adjoins the insulation layer. A passivating substance is present, with the formation of Si—X bonds, in the region of the interface between the insulation layer and the monocrystalline silicon layer. The bond energy of the Si—X bond is greater than the bond energy of an Si—H bond.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: October 25, 2005
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Huttner, Helmut Wurzer, Reinhard Mahnkopf
  • Patent number: 6781180
    Abstract: A trench capacitor for use in a semiconductor memory cell is formed in a substrate and includes a trench having an upper region and a lower region. An insulation collar is formed in the upper region of the trench. The lower region of the trench extends through a buried well. A dielectric layer, which is formed from tungsten oxide, serves as a capacitor dielectric. A conductive trench filling, which is filled into the trench, is formed from silicon or a tungsten-containing material such as tungsten, tungsten silicide or tungsten nitride.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: August 24, 2004
    Assignee: Infineon Technologies AG
    Inventors: Schrems Martin, Dirk Drescher, Helmut Wurzer, Wolfram Karcher
  • Patent number: 6730607
    Abstract: A method of fabricating a barrier layer includes oxidizing a silicon-containing substrate to form a substrate oxide layer on the surface of the substrate, producing an oxygen-impervious layer at an interface between the substrate oxide layer and the substrate, and etching the substrate oxide layer until the underlying oxygen-impervious layer is uncovered.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: May 4, 2004
    Assignee: Infineon Technologies AG
    Inventors: Helmut Wurzer, Martin Schrems, Anke Krasemann, Thomas Pompl
  • Patent number: 6613624
    Abstract: Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel region by an altered work function of the electrons. Transistors in semiconductor circuits having both a memory region and a logic region are fabricated either with different dopings for pMOS and nMOS transistors in the logic region (dual work function) or with a common source/drain electode in the memory region (borderless contact). In the latter case, all the transistors of the semiconductor circuit receive the same gate doping. A method is proposed by which it is possible to realize dual work function and borderless contact on a semiconductor substrate simultaneously in a simple manner.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: September 2, 2003
    Assignee: Infineon Technologies AG
    Inventor: Helmut Wurzer
  • Publication number: 20030152846
    Abstract: A photolithographic mask has the advantage that a combination of dummy structures, whose pattern is imaged into the resist layer, and auxiliary structures, whose pattern is not imaged into the resist layer, makes it possible to achieve a significant improvement in the imaging properties of the main structures which are disposed at an edge of a region containing a multiplicity of main structures. In particular, constrictions at the structures can be significantly reduced or completely avoided and/or a so-called “tilting” of the structures under non-optimum focus conditions is significantly reduced or completely avoided.
    Type: Application
    Filed: January 29, 2003
    Publication date: August 14, 2003
    Inventors: Lothar Bauch, Robert Feurle, Ina Voigt, Helmut Wurzer
  • Publication number: 20030113963
    Abstract: Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel region by an altered work function of the electrons. Transistors in semiconductor circuits having both a memory region and a logic region are fabricated either with different dopings for pMOS and nMOS transistors in the logic region (dual work function) or with a common source/drain electrode in the memory region (borderless contact). In the latter case, all the transistors of the semiconductor circuit receive the same gate doping. A method is proposed by which it is possible to realize dual work function and borderless contact on a semiconductor substrate simultaneously in a simple manner.
    Type: Application
    Filed: July 24, 2002
    Publication date: June 19, 2003
    Inventor: Helmut Wurzer
  • Patent number: 6451676
    Abstract: A method for setting the threshold voltage of a MOS transistor having a gate composed of polysilicon includes the step of implanting germanium ions into the gate composed of polysilicon in order to change the work function of the gate.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: September 17, 2002
    Assignee: Infineon Technologies AG
    Inventors: Helmut Wurzer, Guiseppe Curello
  • Publication number: 20020070414
    Abstract: A semiconductor element with at least one layer of tungsten oxide, optionally in a structured tungsten oxide layer, is described. The semiconductor element is characterized in that the relative premittivity of the tungsten oxide layer is higher than 50.
    Type: Application
    Filed: July 16, 2001
    Publication date: June 13, 2002
    Inventors: Dirk Drescher, Helmut Tews, Martin Schrems, Helmut Wurzer
  • Publication number: 20020068465
    Abstract: The capacitive electrode structure has a semiconductor substrate, a metal oxide layer on the semiconductor substrate, an oxidation inhibiting layer on the metal oxide layer, and an electrode formed on the oxidation inhibiting layer. The oxidation inhibiting layer is substantially impervious to oxygen and prevents oxygen atoms from diffusing into the metal oxide layer.
    Type: Application
    Filed: December 4, 2000
    Publication date: June 6, 2002
    Inventors: Anke Krasemann, Thomas Pompl, Martin Schrems, Helmut Wurzer
  • Publication number: 20020055269
    Abstract: Method for fabricating a barrier layer having the following steps, namely
    Type: Application
    Filed: June 15, 2001
    Publication date: May 9, 2002
    Inventors: Helmut Wurzer, Martin Schrems, Anke Krasemann, Thomas Pompl
  • Publication number: 20010046787
    Abstract: The present invention provides a method for forming a dielectric 1; 7, 8 on a semiconductor substrate 2 having the following steps: implantation of ions into a surface layer of the semiconductor substrate 2, the ions forming a first dielectric layer 7; and performance of a thermal oxidation process for forming a second dielectric layer 8 on the first dielectric layer 7. Consequently, e.g. by the implantation of nitrogen ions into a surface layer of a silicon substrate, the imperfection density of the dielectric formed can be reduced approximately by a factor of 10.
    Type: Application
    Filed: April 18, 2001
    Publication date: November 29, 2001
    Inventors: Martin Kerber, Helmut Wurzer, Thomas Pompl
  • Publication number: 20010023116
    Abstract: A method for setting the threshold voltage of a MOS transistor having a gate composed of polysilicon includes the step of implanting germanium ions into the gate composed of polysilicon in order to change the work function of the gate.
    Type: Application
    Filed: March 19, 2001
    Publication date: September 20, 2001
    Inventors: Helmut Wurzer, Guiseppe Curello
  • Patent number: 6232220
    Abstract: A method for fabricating a semiconductor component having a low contact resistance with respect to heavily doped or siliconized zones in a semiconductor body. Fluorine ions are implanted into the heavily doped or siliconized zone in the vicinity of a contact hole before a titanium layer is applied to the heavily doped or siliconized zone in the vicinity of the contact hole. As a result of the fluorine, any oxide layers present in the contact hole region can be broken up by less titanium, with the result that a thinner titanium layer is sufficient. In addition, the formation of titanium silicide in the contact hole is promoted.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: May 15, 2001
    Assignee: Infineon Technologies AG
    Inventors: Volker Penka, Reinhard Mahnkopf, Helmut Wurzer
  • Patent number: 5849010
    Abstract: An electrosurgical apparatus has a radio-frequency generator (11) with a variable basic power setting and to which a cutting electrode (12) and a neutral electrode (13) are connected. A power measuring device (15) is connected to the electrodes (12, 13) and acts on a regulating stage (16) which is connected to the power regulating input of the radio-frequency generator (11). The number of sparkovers within a predetermined plural number of periods is determined and is set by regulation of the output power of the radio-frequency generator (11) to a constant value which lies beneath twice the predetermined plural number.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: December 15, 1998
    Assignee: Helmut Wurzer
    Inventors: Helmut Wurzer, Rainer Mackel