Abstract: An integrated semiconductor circuit arrangement is provided which comprises a substrate of semiconductor material of one conductivity type, an epitaxial layer of the opposite conductivity type formed on one major surface of the substrate, the epitaxial layer having function elements such as transistors, diodes, resistances, and so forth, formed therein. A least some of these function elements are located in insulated regions provided for them which in the boundary area between the substrate and the epitaxial layer are bounded by a pn junction and which at right angles to this boundary area are bounded by oxide walls which extend through the epitaxial layer to the substrate. The oxide walls are surrounded by a resistor region of the said one conductivity type which extends through the epitaxial layer to the substrate.

Abstract: A process for the production of a locally high inverse current amplification in a preferably double diffused or implanted inversely operated transistor which includes forming a low doped epitaxial layer of one conductivity type on a high doped semiconductor substrate of the same conductivity type, forming a high doped buried region by ion implantation in the epitaxial layer beneath the zone provided for the collector, forming a low doped second region of the opposite conductivity type, above said first region which covers an area substantially wider than said first region and forming a third high doped region in the surface of the epitaxial layer spaced above said first region and having an area smaller than said first region, the first region forming the emitter, the second region forming the base and the third region forming the collector, the second region extending to the surface surrounding said third region and partially surrounding the first region.

Abstract: A semiconductor device having one or more electrodes thereon composed of doped polycrystalline silicon. Initially undoped polycrystalline silicon is applied at select electrode positions of a semiconductor device and is then doped by diffusion or implantation. The resultant device is characterized by a high current amplification, a low inner path of resistance and low noise.

Abstract: A process for suppressing parasitic components, in particular parasitic diodes and transistors, in integrated circuits which have, in particular, inversely operated transistors, in which a semiconductor substrate of the first conductivity type as introduced therein a highly doped zone of a second conductivity type which is opposite to the first conductivity type and which extends to a surface of the semiconductor substrate. A semiconductor layer of the second conductivity type is epitaxially deposited on the surface and the semiconductor layer further has produced therein zones of differing conductivity type which form at least one component which is electrically insulated from adjacent components.

Abstract: A semiconductor body is coated at selected areas thereof with a polycrystalline or amorphous semiconductor layer, a dopant is ion-implanted into such polycrystalline or amorphous layer and the resultant structure is then subjected to diffusion conditions to diffuse the dopant from the polycrystalline or amorphous layer into the select zone of the semiconductor body. This process causes very slight disturbances in the crystal lattice of the semiconductor body and provides an adjustable dopant concentration at select surface zones of the semiconductor body.

Abstract: A process for producing an inversely operated transistor in a body of semiconductor material which has arranged on its surface collector, base and emitter zones and wherein the base is doped by ion implantation so that minority charge carriers injected from the emitter zone into the base zone are accelerated in the direction towards the collector zone due to an inner drift field in the base zone.

Abstract: The "emitter-dip effect" is eliminated by applying a layer of an undoped polycrystalline semiconductor onto the surface of a select zone to be doped in a semiconductor body, for example, such as on the emitter zone of a silicon body and then diffusing a select dopant through the undoped polycrystalline semiconductor layer into the select zone of the semiconductor body.

Abstract: A combination insulating means comprised of a pn-junction overlaid with a SiO.sub.2 filling within a groove is provided between IC elements in a monolithic semiconductor device. Such combination insulating means electrically and mechanically isolate at least two areas of a n-conductive surface zone, each of which supports an IC element. The n-conductive surface zone is supported on a p-conductive silicon base and the free surface of the n-conductive surface zone is coated with a Si.sub.3 N.sub.4 layer, which during the various fabrication steps of the monolithic semiconductor device protects coated areas of the n-conductive surface zone from etchants, oxidation and from dopants.

Abstract: A ring or lattice-shaped groove or trench is etched into a surface of a Si monocrystal layer. At least one boundary of the so-etched groove or trench is coated with a strip-shaped layer of an oxidation-blocking material, such as Si.sub.3 N.sub.4 and the area of the substrate adjacent to the Si.sub.3 N.sub.4 layer and/or the substrate area enclosed by such layer is provided with a relatively thick SiO.sub.2 layer which extends deeper into the Si surface than does the SiN.sub.4 layer, while the Si surface within the groove or trench remains uncoated. The so-obtained arrangement is then thermally oxidized under conditions sufficient to at least partially fill the groove or trench with SiO.sub.2. Thereafter, the oxidation-blocking layer and at least a part of the SiO.sub.2 layer which is outside the ring or lattice-shaped trench is removed by a suitable etchant from the monocrystalline surface and the thus uncovered Si surface is further processed to produce small pn-junctions.

Abstract: The surface of a semiconductor substrate, such as a silicon crystal, is uniformly coated with a layer of Si.sub.3 N.sub.4 and at least two selectively spaced windows are provided therein. The uncovered silicon surface within such windows is then coated with a layer of SiO.sub.2. Next, a SiO.sub.2 area within a first window along with a portion of the adjacent Si.sub.3 N.sub.4 areas are coated with a photo-lacquer mask while the substrate surface area beneath the second window is doped with a select dopant. This procedure is then reversed and the Photo-lacquer mask is removed from the first window and applied onto the second window while the substrate surface area beneath the first window is contacted with select dopant to produce a doped zone. In this manner, considerable tolerance for positioning of a diffusion mask is provided.