Abstract: A lateral DMOS transistor structure formed in N-type silicon is disclosed which incorporates a special N-type enhanced drift region. In one embodiment, a cellular transistor with a polysilicon gate mesh is formed over an N epitaxial layer with P body regions, P.sup.+ body contact regions, N.sup.+ source and drain regions, and N enhanced drift regions. The N enhanced drift regions are more highly doped than the epitaxial layer and extend between the drain regions and the gate. Metal strips are used to contact the rows of source and drain regions. The N enhanced drift regions serve to significantly reduce on-resistance without significantly reducing breakdown voltage.

Abstract: A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

Abstract: One embodiment of the invention includes multiple patterns on a single mask, where all the patterns on the single mask are used for forming a single product. In the preferred embodiment, each of four quadrants of a mask have a different process layer pattern, where each of the four patterns is associated with a different process layer for the same product. After exposure of the wafer using the mask, the mask is rotated 90.degree. for the next exposure step so that the mask pattern image for the next layer to be formed on the wafer will overlie the designated quadrant of the wafer which will contain the final product. Although, by using this technique, three-quarters of the wafer will be unusable, this partial waste of the wafer will be offset by the savings in mask costs with low volume production, in prototyping situations, and in product debugging. Using the above technique, conventional mask exposure machines may be used.

Abstract: A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.