Abstract: A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.

Abstract: In one embodiment, a method for compiling an HDL specification for simulation of a circuit design is provided. Using one or more processors the circuit design is elaborated from the HDL specification. Two or more instances of a module of the elaborated design that have a same hardware configuration are determined. Simulation code that models the circuit design is generated. A first portion of the simulation code is configured to model the module having the hardware configuration. For each of the two or more instances, a second portion of the simulation code is configured to, in response to an indication to simulate the instance, execute the first portion of simulation code using a respective set of nets corresponding to the instance.

Abstract: Processing a circuit design can include determining a first set of net sensitivity ranges for a net of the circuit design, wherein at least two net sensitivity ranges of the first set are partially overlapping, and translating the first set of net sensitivity ranges into a second set of net sensitivity ranges comprising a plurality of member net sensitivity ranges with no partially overlapping member net sensitivity ranges. A net sensitivity tree can be constructed that includes hierarchically ordered nodes. Each node can specify a net sensitivity range of one member of the second set of net sensitivity ranges.

Abstract: A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.

Abstract: In one embodiment, a method is provided for generating dataflow-driven simulation code of a circuit design described with a combination of first and second HDLs. The circuit description is elaborated and a simulation dataflow graph of the circuit description is generated. Simulation code, configured to model execution of the design in a data-driven manner according to the simulation dataflow graph, is generated from the dataflow graph using a first HDL signal representation having a format compatible with the first HDL and a second HDL signal representation having a format compatible with the second HDL. For each instantiated module of the circuit description at a cross language boundary in the simulation dataflow graph, ports of the instantiated module are mapped to the first HDL signal representation and mapped to the second HDL signal representation.

Abstract: One or more embodiments provide a method of HDL simulation that determines dependencies, forcing characteristics, and strength characteristics of nets for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

Abstract: A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.

Abstract: During the elaboration and synthesis of a circuit design, a parse tree generally must be fully expanded to access memory resources and data of individual module instances in order to perform optimizations that will result in better runtime performance of generated simulation code. The present invention reduces memory requirements in generating simulation or emulation executable code by implementing a collapsed parse tree, where multiple instances of a module in a HDL design are represented by a single representative node in the parse tree.

Abstract: One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc., for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

Abstract: Approaches for generating functions for activating processes in a simulation model. At least two mutually exclusive sub-ranges of a plurality of bits of a net of the circuit design are determined. A respective process set associated with each sub-range of the plurality of bits is determined. The specification of a wakeup function includes for each sub-range of the plurality of bits, a test for a change in value of at least one bit in the sub-range of the plurality of bits, and an initiation of each process in the associated process set in response to a detected change in value of the at least one bit. The specification also includes control, responsive to a detected change in value of at least one bit in one of the sub-ranges, that bypasses a test for a change in value of at least one bit in at least one other of the sub-ranges.

Abstract: Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.

Abstract: The present invention provides a method, system and article of manufacture for the transformation of parallel blocks into synchronized parallel processes that can be simulated without incurring the overhead of creating extra threads or requiring code modifications in the simulation kernel. This transformation is done in such a way that the parallel behavior is retained in its entirety, and the same simulation time-relative results are produced. The concept of concurrency of processes inherent in HDL languages, including System Verilog, is utilized to achieve the same simulation results via the transformed HDL code, which uses the non-parallel block subset of System Verilog HDL.

Abstract: A method of securing a circuit design can include generating a string including a plurality of elements. The plurality of elements can include elements of design information selected from within the circuit design and at least one security element indicating whether the circuit design is protected. The method further can include permuting the plurality of elements of the string, encrypting the permuted string using a key shared with a circuit design tool, and including the permuted and encrypted string within the circuit design.

Abstract: A method of creating a secure intellectual property (IP) representation of a circuit design for use with a software-based simulator can include translating a hardware description language representation of the circuit design into an encrypted intermediate form and compiling the intermediate form of the circuit design to produce encrypted object code. The method further can include linking the encrypted object code with a simulation kernel library thereby creating the secure IP representation of the circuit design. The secure IP can include an encrypted simulation model of the circuit design and a simulation kernel configured to execute the encrypted simulation model.