Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers.

Abstract: Dead cycles are removed from an upstream side of a data communications bus. In one example, data symbols are received on clock cycles from lanes of a peripheral device bus having dead cycles. The data symbols are sent upstream on the clock cycles. The start of a packet in the received data symbols is detected and the sending of the data symbols is stalled before sending the start of the packet until additional cycles of data are written into a buffer. Logical idle symbols are sent upstream in place of the data during the stalling. The start of the packet sent after the additional cycles of data are read into the buffer. When a dead cycle is detected during the packet, then a buffered cycle of data is sent upstream during the dead cycle.

Abstract: According to one embodiment, an apparatus includes a transaction data storage to store transaction data to be transmitted over an interconnect of a data processing system, a transaction buffer coupled to the transaction data storage to buffer at least a portion of the transaction data, and a transaction logic coupled to the transaction data storage and the transaction buffer to transmit a request (REQ) signal to an arbiter associated with the interconnect in response to first transaction data that becomes available in the transaction data storage, in response to a grant (GNT) signal received from the arbiter, retrieve second transaction data from the transaction buffer and transmit the second transaction data onto the interconnect, and refill the transaction buffer with third transaction data retrieved from the transaction data storage after the second transaction data has been transmitted onto the interconnect.

Abstract: Dead cycles are removed from an upstream side of a data communications bus. In one example, data symbols are received on clock cycles from lanes of a peripheral device bus having dead cycles. The data symbols are sent upstream on the clock cycles. The start of a packet in the received data symbols is detected and the sending of the data symbols is stalled before sending the start of the packet until additional cycles of data are written into a buffer. Logical idle symbols are sent upstream in place of the data during the stalling. The start of the packet sent after the additional cycles of data are read into the buffer. When a dead cycle is detected during the packet, then a buffered cycle of data is sent upstream during the dead cycle.

Abstract: According to one embodiment, an apparatus includes a transaction data storage to store transaction data to be transmitted over an interconnect of a data processing system, a transaction buffer coupled to the transaction data storage to buffer at least a portion of the transaction data, and a transaction logic coupled to the transaction data storage and the transaction buffer to transmit a request (REQ) signal to an arbiter associated with the interconnect in response to first transaction data that becomes available in the transaction data storage, in response to a grant (GNT) signal received from the arbiter, retrieve second transaction data from the transaction buffer and transmit the second transaction data onto the interconnect, and refill the transaction buffer with third transaction data retrieved from the transaction data storage after the second transaction data has been transmitted onto the interconnect.