Patents by Inventor Hema C. Nalluri
Hema C. Nalluri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359499Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.Type: ApplicationFiled: May 9, 2023Publication date: November 9, 2023Inventors: James VALERIO, Vasanth RANGANATHAN, Joydeep RAY, Rahul A. KULKARNI, Abhishek R. APPU, Jeffery S. BOLES, Hema C. NALLURI
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Patent number: 11726826Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.Type: GrantFiled: June 4, 2021Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: James Valerio, Vasanth Ranganathan, Joydeep Ray, Rahul A. Kulkarni, Abhishek R. Appu, Jeffery S. Boles, Hema C. Nalluri
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Publication number: 20220129323Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.Type: ApplicationFiled: June 4, 2021Publication date: April 28, 2022Inventors: James VALERIO, Vasanth RANGANATHAN, Joydeep RAY, Rahul A. KULKARNI, Abhishek R. APPU, Jeffery S. BOLES, Hema C. NALLURI
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Patent number: 11145115Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.Type: GrantFiled: December 27, 2018Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Murali Ramadoss, Balaji Vembu, Hema C. Nalluri, Michael Apodaca, Jeffery S. Boles
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Patent number: 11074109Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.Type: GrantFiled: March 27, 2019Date of Patent: July 27, 2021Assignee: Intel CorporationInventors: James Valerio, Vasanth Ranganathan, Joydeep Ray, Rahul A. Kulkarni, Abhishek R. Appu, Jeffery S. Boles, Hema C. Nalluri
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Patent number: 10908939Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics engType: GrantFiled: January 31, 2017Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Balaji Vembu, Altug Koker, David Puffer, Murali Ramadoss, Bryan R. White, Hema C. Nalluri, Aditya Navale
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Patent number: 10885880Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.Type: GrantFiled: December 11, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Jeffery S. Boles, Hema C. Nalluri, Balaji Vembu, Michael Apodaca, Altug Koker, Lalit K. Saptarshi
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Publication number: 20200310883Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Inventors: James VALERIO, Vasanth RANGANATHAN, Joydeep RAY, Rahul A. KULKARNI, Abhishek R. APPU, Jeffery S. BOLES, Hema C. NALLURI
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Patent number: 10789071Abstract: Systems, apparatuses and methods may provide for associating a first instruction pointer with an IF block of a primary IF-ELSE conditional construct associated with a thread and activating a second instruction pointer in response to a dependency associated with the IF block. Additionally, the second instruction pointer may be associated with an ELSE block of the primary IF-ELSE conditional construct. In one example, the IF block and the ELSE block are executed, via the first instruction pointer and the second instruction pointer, one or more of independently from or parallel to one another.Type: GrantFiled: July 8, 2015Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Hema C. Nalluri, Supratim Pal, Subramaniam Maiyuran, Joy Chandra
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Publication number: 20200193940Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.Type: ApplicationFiled: December 11, 2019Publication date: June 18, 2020Inventors: JEFFERY S. BOLES, HEMA C. NALLURI, BALAJI VEMBU, MICHAEL APODACA, ALTUG KOKER, LALIT K. SAPTARSHI
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Patent number: 10672176Abstract: An apparatus and method are described for culling commands in a tile-based renderer. For example, one embodiment of an apparatus comprises: a command buffer to store a plurality of commands to be executed by a render pipeline to render a plurality of tiles; visibility analysis circuitry to determine per-tile visibility information for each of the plurality of tiles and to store the visibility information for a first tile in a first storage, the visibility information specifying either that all of the commands associated with rendering the first tile can be skipped or identifying individual commands associated with rendering the first tile that can be skipped; and a render pipeline to read the visibility information from the first storage to determine whether to execute or skip one or more of the commands from the command buffer to render the first tile.Type: GrantFiled: August 31, 2017Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Hema C. Nalluri, Balaji Vembu, Peter L. Doyle, Michael Apodaca, Jeffery S. Boles
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Patent number: 10522114Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.Type: GrantFiled: May 30, 2018Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Jeffery S. Boles, Hema C. Nalluri, Balaji Vembu, Michael Apodaca, Altug Koker, Lalit K. Saptarshi
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Patent number: 10303902Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged.Type: GrantFiled: April 24, 2017Date of Patent: May 28, 2019Assignee: INTEL CORPORATIONInventors: Hema C. Nalluri, Aditya Navale, Murali Ramadoss
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Publication number: 20190130635Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.Type: ApplicationFiled: December 27, 2018Publication date: May 2, 2019Inventors: Murali Ramadoss, Balaji Vembu, Hema C. Nalluri, Michael Apodaca, Jeffery S. Boles
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Publication number: 20190066354Abstract: An apparatus and method are described for culling commands in a tile-based renderer. For example, one embodiment of an apparatus comprises: a command buffer to store a plurality of commands to be executed by a render pipeline to render a plurality of tiles; visibility analysis circuitry to determine per-tile visibility information for each of the plurality of tiles and to store the visibility information for a first tile in a first storage, the visibility information specifying either that all of the commands associated with rendering the first tile can be skipped or identifying individual commands associated with rendering the first tile that can be skipped; and a render pipeline to read the visibility information from the first storage to determine whether to execute or skip one or more of the commands from the command buffer to render the first tile.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Inventors: HEMA C. NALLURI, BALAJI VEMBU, PETER L. DOYLE, MICHAEL APODACA, JEFFERY S. BOLES
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Patent number: 10210655Abstract: By scheduling/managing workload submission to a position only shading pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments. An interface submits workloads to a slave engine running in one parallel pipe to assist a main engine running in another parallel pipe. Command sequences for each parallel pipe are separated to enable the slave engine to run ahead of the main engine. The slave engine is a position only shader and the main engine is a render engine.Type: GrantFiled: September 25, 2015Date of Patent: February 19, 2019Assignee: Intel CorporationInventors: Murali Ramadoss, Balaji Vembu, Hema C. Nalluri, Michael Apodaca, Jeffery S. Boles
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Patent number: 10192281Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.Type: GrantFiled: July 7, 2016Date of Patent: January 29, 2019Assignee: INTEL CORPORATIONInventors: Jeffery S. Boles, Hema C. Nalluri, Balaji Vembu, Pritav H. Shah, Michael Apodaca, Murali Ramadoss, Lalit K. Saptarshi
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Publication number: 20180286009Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.Type: ApplicationFiled: May 30, 2018Publication date: October 4, 2018Inventors: JEFFERY S. BOLES, HEMA C. NALLURI, BALAJI VEMBU, MICHAEL APODACA, ALTUG KOKER, LALIT K. SAPTARSHI
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Patent number: 10068307Abstract: The same set of render commands can be re-executed for each of a plurality of tiles making up a graphic scene to be rendered. Each time the list of commands is executed, the way the commands are executed may be modified based on information received from tile pre-processing. Specifically, a jump if command may be inserted into the command list. When this command is encountered, a determination is made, based on information received from tile pre-processing pipeline, whether to execute the command for the next primitive or not. If the next primitive is to be culled then the command for the next primitive is not executed and the flow moves past that command. If the next primitive is to be executed then the jump is not implemented. This enables avoiding reloading the same list of commands over and over for every tile.Type: GrantFiled: May 20, 2016Date of Patent: September 4, 2018Assignee: Intel CorporationInventors: Balaji Vembu, Peter L. Doyle, Michael Apodaca, Hema C. Nalluri, Jeffery S. Boles
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Publication number: 20180218530Abstract: An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics engType: ApplicationFiled: January 31, 2017Publication date: August 2, 2018Inventors: BALAJI VEMBU, ALTUG KOKER, DAVID PUFFER, MURALI RAMADOSS, BRYAN R. WHITE, HEMA C. NALLURI, ADITYA NAVALE