Patents by Inventor Hema Nalluri
Hema Nalluri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230039853Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Intel CorporationInventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler
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Patent number: 11481864Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.Type: GrantFiled: April 19, 2021Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler
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Publication number: 20220222340Abstract: Security and support for trust domain operation is described. An example of a method includes processing, at an accelerator, one or more compute workloads received from a host system; upon receiving a notification that a trust domain has transitioned to a secure state, transition an original set of privileges for the accelerator to a downgraded set of privileges; upon receiving a command from the host system for the trust domain, processing the command in accordance with the trust domain; and upon receiving a request from the host system to access a register, for a register included in an allowed list of registers for access, allow access to the register, and, for a register that is not within the allowed list of registers for access, disallowing access to the register.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Applicant: Intel CorporationInventors: Vidhya Krishnan, Ankur Shah, Bryan White, Daniel Nemiroff, David Puffer, Julien Carreno, Scott Janus, Ravi Sahita, Hema Nalluri, Utkarsh Y. Kakaiya
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Publication number: 20210241418Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.Type: ApplicationFiled: April 19, 2021Publication date: August 5, 2021Applicant: Intel CorporationInventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler
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Patent number: 10997686Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.Type: GrantFiled: January 9, 2019Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler
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Patent number: 10796472Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.Type: GrantFiled: June 30, 2018Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Michael Apodaca, Ankur Shah, Ben Ashbaugh, Brandon Fliflet, Hema Nalluri, Pattabhiraman K, Peter Doyle, Joseph Koston, James Valerio, Murali Ramadoss, Altug Koker, Aditya Navale, Prasoonkumar Surti, Balaji Vembu
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Publication number: 20200219223Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.Type: ApplicationFiled: January 9, 2019Publication date: July 9, 2020Applicant: Intel CorporationInventors: Balaji Vembu, Brandon Fliflet, James Valerio, Michael Apodaca, Ben Ashbaugh, Hema Nalluri, Ankur Shah, Murali Ramadoss, David Puffer, Altug Koker, Aditya Navale, Abhishek R. Appu, Joydeep Ray, Travis Schluessler
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Patent number: 10579382Abstract: An apparatus and method for scalable interrupt reporting.Type: GrantFiled: January 24, 2018Date of Patent: March 3, 2020Assignee: Intel CorporationInventors: Rajesh Sankaran, Ankur Shah, Bryan White, Hema Nalluri, David Puffer, Murali Ramadoss, Altug Koker, Aditya Navale, Balaji Vembu
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Publication number: 20200005516Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.Type: ApplicationFiled: June 30, 2018Publication date: January 2, 2020Inventors: MICHAEL APODACA, ANKUR SHAH, BEN ASHBAUGH, BRANDON FLIFLET, HEMA NALLURI, PATTABHIRAMAN K, PETER DOYLE, JOSEPH KOSTON, JAMES VALERIO, MURALI RAMADOSS, ALTUG KOKER, ADITYA NAVALE, PRASOONKUMAR SURTI, BALAJI VEMBU
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Patent number: 10410311Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.Type: GrantFiled: March 7, 2016Date of Patent: September 10, 2019Assignee: INTEL CORPORATIONInventors: Balaji Vembu, Kritika Bala, Murali Ramadoss, Hema Nalluri, Jeffery Boles, Jeffrey Frizzell, Joseph Koston
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Publication number: 20190227801Abstract: An apparatus and method for scalable interrupt reporting.Type: ApplicationFiled: January 24, 2018Publication date: July 25, 2019Inventors: RAJESH SANKARAN, ANKUR SHAH, BRYAN WHITE, HEMA NALLURI, DAVID PUFFER, MURALI RAMADOSS, ALTUG KOKER, ADITYA NAVALE, BALAJI VEMBU
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Publication number: 20170256019Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.Type: ApplicationFiled: March 7, 2016Publication date: September 7, 2017Applicant: Intel CorporationInventors: Balaji Vembu, Kritika Bala, Murali Ramadoss, Hema Nalluri, Jeffery Boles, Jeffrey Frizzell, Joseph Koston