Abstract: Pre-comparing data in a dual compare content compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. A first compare input and a second compare input of a column in a dual compare content addressable memory (“CAM”) device. A pre-compare signal is generated based on comparing the first compare input and the second compare input. A first polarity of the first compare input is compared with a first polarity a storage node data. A compare output of the first compare input is generated based on a logic state of the pre-compare signal. A first compare match is generated based on the compare output and a second compare match is generated based on the pre-compare signal.

Abstract: A compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. The CAM devices includes a transmission gate, having a positive field effect transistor (“PFET”) and a negative field effect transistor (“NFET”), configured to compare a compare data input with storage node data having a first logic state. The CAM devices includes a passgate, in communication with the transmission gate, configured to compare the compare data input having a first logic state with the storage node data having a second logic state, wherein the passgate is an n-channel metal oxide semiconductor (NMOS) transistor and controls propagation of the compare data input, and the storage node data of a storage cell is used to control the passgate based on the storage node data. The CAM devices includes a PFET stack, having a first PFET and a second PFET, in communication with the transmission gate and the passgate, configured to compare the compare data input with the storage node data having the second logic state.

Abstract: Pre-comparing data in a dual compare content compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. A first compare input and a second compare input of a column in a dual compare content addressable memory (“CAM”) device. A pre-compare signal is generated based on comparing the first compare input and the second compare input. A first polarity of the first compare input is compared with a first polarity a storage node data. A compare output of the first compare input is generated based on a logic state of the pre-compare signal. A first compare match is generated based on the compare output and a second compare match is generated based on the pre-compare signal.

Abstract: A compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. The CAM devices includes a transmission gate, having a positive field effect transistor (“PFET”) and a negative field effect transistor (“NFET”), configured to compare a compare data input with storage node data having a first logic state. The CAM devices includes a passgate, in communication with the transmission gate, configured to compare the compare data input having a first logic state with the storage node data having a second logic state, wherein the passgate is an n-channel metal oxide semiconductor (NMOS) transistor and controls propagation of the compare data input, and the storage node data of a storage cell is used to control the passgate based on the storage node data. The CAM devices includes a PFET stack, having a first PFET and a second PFET, in communication with the transmission gate and the passgate, configured to compare the compare data input with the storage node data having the second logic state.

Abstract: At least one method, apparatus and system disclosed involves a memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

Abstract: A memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

Abstract: A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.

Abstract: A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled to the precharge circuit that enables the precharge circuit at a beginning portion of a read cycle, keeps the precharge circuit disabled until an end of the read cycle, and keeps the precharge circuit disabled during a write cycle. A method of operating a memory, in which the memory includes an array of memory cells coupled to bit lines, includes precharging the bit lines at a beginning of a read cycle. The method also includes blocking precharging of the bit lines for a duration of a write cycle.

Abstract: A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.

Abstract: A memory having a memory array having bit cells coupled to bit lines. The memory further includes a precharge circuit that precharges bit lines. The memory also includes a control circuit coupled to the precharge circuit that enables the precharge circuit at a beginning portion of a read cycle, keeps the precharge circuit disabled until an end of the read cycle, and keeps the precharge circuit disabled during a write cycle. A method of operating a memory, in which the memory includes an array of memory cells coupled to bit lines, includes precharging the bit lines at a beginning of a read cycle. The method also includes blocking precharging of the bit lines for a duration of a write cycle.

Abstract: A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.

Abstract: A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.

Abstract: A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.

Abstract: A memory has bits that fail as power supply voltage is reduced to reduce power and/or increase endurance. The bits become properly functional when the power supply voltage is increased back to its original value. With the reduced voltage, portions of the memory that include non-functional bits are not used. Much of the memory may remain functional and use is retained. When the voltage is increased, the portions of the memory that were not used because of being non-functional due to the reduced power supply voltage may then be used again. This is particularly useful in a cache where the decrease in available memory due to power supply voltage reduction can be implemented as a reduction in the number of ways. Thus, for example an eight way cache can simply be reduced to a four way cache when the power is being reduced or endurance increased.

Abstract: A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, including a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.

Abstract: A method for dynamically controlling sense amplifier differential margin of a memory during operation, in an integrated circuit, comprising a plurality of addressable units, is provided. The method includes setting the sense amplifier differential margin corresponding to the plurality of addressable units to a first value. The method further includes if a read data error occurs when data is read from a set of the plurality of addressable units, then setting the sense amplifier differential margin corresponding to the plurality of addressable units to a second value, wherein the second value is greater than the first value.

Abstract: A method and apparatus for detecting faults in digital, analog, and hybrid integrated circuits is disclosed. A single test vector employing bias voltage on input used in conjunction with pulsing the power supply rails is used to allow detection of the various faults which may be present. The instantaneous rail current (i.sub.DD) is then employed for analysis of the circuit, preferably by neural network.