Patents by Inventor Hemang Maheshkumar Parekh

Hemang Maheshkumar Parekh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7793200
    Abstract: A method of accessing a memory of a trellis decoder. The method comprises the steps of writing a first block of data associated with a trellis function to a first memory block; writing a second block of data associated with the trellis function to a second memory block; simultaneously writing a third block of data to a third memory block and reading the second block of data from the second memory block to generate training data; and simultaneously reading data to be decoded from the first memory block and writing a fourth block of data to the first memory block and generating training data associated with the third block of data. A circuit for accessing a memory of a trellis decoder is also described.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: September 7, 2010
    Assignee: Xilinx, Inc.
    Inventors: Hemang Maheshkumar Parekh, Elizabeth R. Cowie, Jeffrey Allan Graham, Hai-Jo Tarn, Vanessa Yi-Mei Chou
  • Patent number: 7669017
    Abstract: A method of buffering data in a circuit processing data in both a natural address order and a modified address order is described. The method comprises the steps of storing a first block of data according to a first addressing order of a natural address order or a modified address order; reading the first block of data stored in a buffer according to the other addressing order of the natural address order and the modified address order; and simultaneously writing a second block of data to the buffer in the other addressing order while reading the first block of data stored in a buffer according to the other addressing order.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: February 23, 2010
    Assignee: Xilinx, Inc.
    Inventors: Hemang Maheshkumar Parekh, Hai-Jo Tarn, Gabor Szedo, Vanessa Yu-Mei Chou, Jeffrey Allan Graham, Elizabeth R. Cowie
  • Patent number: 7610453
    Abstract: Each array in a sequence of arrays is reordered. A first port receives in a first serial order a number of values in each array in the sequence and a second port transmits the values in a different second serial order. For each value in each array in the sequence, the address generator generates an address within a range of zero through one less than the number of values in the array. For each address from the generator, the memory performs an access to a location corresponding to the address in the memory. The access for each address includes a read from the location before a write to the location. For each array in the sequence, the writes for the addresses serially write the values of the array in the first serial order and the reads for the addresses serially read the values in the second serial order.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: October 27, 2009
    Assignee: Xilinx, Inc.
    Inventors: Hemang Maheshkumar Parekh, Jeffrey Allan Graham, Hai-Jo Tarn, Elizabeth R. Cowie, Vanessa Yi-Mei Chou