Abstract: An integrated circuit memory includes memory cells 2 is connected to a power supply Vdd via a power supply control circuit 4. The power supply control circuit includes a first gate 26 and a second gate 28. The first gate 26 is switched by a write assist circuit so as to be non-conductive when writing to the memory cell 2. The second gate 28 is conductive both when writing to the memory cell 2 and when not writing to the memory cell 2. Accordingly, when a write operation is made a relatively high resistance path is formed through the power supply control circuit 4 compared to when writing is not being performed. This increase in the resistance through the power supply control circuit 4 during write operations induces a dip in the virtual supply voltage provided at the supply output of the power supply control circuit 4 in a manner which assist writes to be made.