Patents by Inventor Hemanshu Bhatt

Hemanshu Bhatt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220021221
    Abstract: One example provides a system for dynamically balancing power in a battery pack during charging and discharging. The system includes a battery pack, a control unit, and a load unit. The battery pack includes one or more modules. Each module includes one or more bricks. Each brick includes one or more blocks connected either in a series configuration or in a parallel configuration. Each block includes one or more cells. The control unit is connected with the battery pack across each of the blocks for processing power from each of the blocks irrespective of a power mismatch between the blocks. The control unit dynamically balances the power in the battery pack by controlling a differential current from a block with higher state of charge (SOC) to a block of lower SOC, using one or more converters and thereby maximizing available energy of the battery pack during charging and discharging.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Inventors: Sunit Tyagi, Jitendra Apte, Hemanshu Bhatt, Anupam Hudait, Ranjith N, Pooja Sharma, Dipti Kapadia, Rashmi Naroji, Bhavin Shah, Deepthi Keshavan
  • Patent number: 11183839
    Abstract: Disclosed examples relate to a power conversion system configured to provide a power output from an arrangement of direct current (DC) power sources. One example power conversion system includes multiple power sources PV(n), n=1 to x, connected in a series. For each power source PV(n) for n=1 to x?1, the power conversion system includes an intermediate bidirectional voltage converter VC(n) connected to a first terminal of the power source PV(n), a first terminal of power source PV(x), and a second terminal of power source PV(1). Each intermediate bidirectional voltage converter VC(n) includes a first switch operable in a pulsed mode to boost a power output by power source PV(n) and a second switch operable in a pulsed mode to reduce a power output by power source PV(n). The power conversion system also includes a balancer VC(x) connected to the first terminal of PV(x) and to a load.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: November 23, 2021
    Assignee: IGRENENERGI, INC.
    Inventors: Jitendra Apte, Alok Srivastava, Hemanshu Bhatt, Sunit Tyagi, Dipti Kapadia, Vinod Kumar Singh, Bhawani Patnaik, Leah Mathew
  • Publication number: 20180102646
    Abstract: Disclosed examples relate to a power conversion system configured to provide a power output from an arrangement of direct current (DC) power sources. One example power conversion system includes multiple power sources PV(n), n=1 to x, connected in a series. For each power source PV(n) for n=1 to x?1, the power conversion system includes an intermediate bidirectional voltage converter VC(n) connected to a first terminal of the power source PV(n), a first terminal of power source PV(x), and a second terminal of power source PV(1). Each intermediate bidirectional voltage converter VC(n) includes a first switch operable in a pulsed mode to boost a power output by power source PV(n) and a second switch operable in a pulsed mode to reduce a power output by power source PV(n). The power conversion system also includes a balancer VC(x) connected to the first terminal of PV(x) and to a load.
    Type: Application
    Filed: October 10, 2017
    Publication date: April 12, 2018
    Inventors: Jitendra Apte, Alok Srivastava, Hemanshu Bhatt, Sunit Tyagi, Dipti Kapadia, Vinod Kumar Singh, Bhawani Patnaik, Leah Mathew
  • Patent number: 9577548
    Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: February 21, 2017
    Assignee: IgrenEnergi, Inc.
    Inventors: Sunit Tyagi, Hemanshu Bhatt
  • Publication number: 20140030541
    Abstract: Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can he provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.
    Type: Application
    Filed: October 3, 2013
    Publication date: January 30, 2014
    Applicant: LSI CORPORATION
    Inventors: Hemanshu Bhatt, Dilip Vijay, Jayanthi Pallinti, Sey-Shing Sun, Hong Ying, Chi-Yi Kao
  • Publication number: 20140008987
    Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 9, 2014
    Applicant: igrenEnergi Semiconductor Technologies Pvt. Ltd.
    Inventors: Sunit Tyagi, Hemanshu Bhatt
  • Patent number: 8552560
    Abstract: Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 8, 2013
    Assignee: LSI Corporation
    Inventors: Hemanshu Bhatt, Dilip Vijay, Jayanthi Pallinti, Sey-Shing Sun, Hong Ying, Chiyi Kao
  • Patent number: 8552587
    Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: October 8, 2013
    Assignee: igrenEnergi Semiconductor Technologies Pvt. Ltd.
    Inventors: Sunit Tyagi, Hemanshu Bhatt
  • Publication number: 20120019072
    Abstract: Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 26, 2012
    Applicant: INSOLARE ENERGY PRIVATE LIMITED
    Inventors: Sunit Tyagi, Hemanshu Bhatt
  • Patent number: 8076779
    Abstract: A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 ?m aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 ?m. Another possibility is provide an extra 0.6 ?m aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 ?m aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 ?m and another barrier layer of 60 nm.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: December 13, 2011
    Assignee: LSI Corporation
    Inventors: Sey-Shing Sun, Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Hong Ying, Chiyi Kao, Peter Burke
  • Patent number: 7955919
    Abstract: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: June 7, 2011
    Assignee: LSI Corporation
    Inventors: David Pritchard, Hemanshu Bhatt, David T. Price
  • Patent number: 7531442
    Abstract: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: May 12, 2009
    Assignee: LSI Corporation
    Inventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao, Peter Burke, Ramaswamy Ranganathan, Qwai Low
  • Publication number: 20080102583
    Abstract: A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.
    Type: Application
    Filed: December 19, 2007
    Publication date: May 1, 2008
    Applicant: LSI LOGIC CORPORATION
    Inventors: David Pritchard, Hemanshu Bhatt, David Price
  • Publication number: 20070259518
    Abstract: A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
    Type: Application
    Filed: December 29, 2005
    Publication date: November 8, 2007
    Inventors: Derryl Allman, Hemanshu Bhatt, Charles May, Peter Burke, Byung-Sung Kwak, Sey-Shing Sun, David Price, David Pritchard
  • Publication number: 20070254448
    Abstract: An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.
    Type: Application
    Filed: June 11, 2007
    Publication date: November 1, 2007
    Inventors: Hemanshu Bhatt, Jan Fure, Derryl Allman
  • Publication number: 20070155160
    Abstract: A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 5, 2007
    Inventors: Derryl Allman, Hemanshu Bhatt, Charles May, Peter Burke, Byung-Sung Kwak, Sey-Shing Sun, David Price, David Pritchard
  • Publication number: 20070123024
    Abstract: Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
    Type: Application
    Filed: November 30, 2005
    Publication date: May 31, 2007
    Inventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao, Peter Burke, Ramaswamy Ranganathan, Qwai Low
  • Publication number: 20070114667
    Abstract: Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.
    Type: Application
    Filed: November 18, 2005
    Publication date: May 24, 2007
    Inventors: Hemanshu Bhatt, Dilip Vijay, Jayanthi Pallinti, Sey-Shing Sun, Hong Ying, Chiyi Kao
  • Publication number: 20070102812
    Abstract: A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 ?m aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 ?m. Another possibility is provide an extra 0.6 ?m aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 ?m aluminum layer, followed by another barrier layer of 60 nm, another aluminum layer of 0.6 ?m and another barrier layer of 60 nm.
    Type: Application
    Filed: November 8, 2005
    Publication date: May 10, 2007
    Inventors: Sey-Shing Sun, Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Hong Ying, Chiyi Kao, Peter Burke
  • Patent number: 7205673
    Abstract: A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: April 17, 2007
    Assignee: LSI Logic Corporation
    Inventors: Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao