Abstract: The present invention provides a method of forming a dielectric on a semiconductor substrate. A dielectric is grown at a substrate interface in a plurality of increments. Stress is relieved at the dielectric substrate interface between each increment. In another aspect, stress relief is performed by annealing the substrate. The annealing is performed by placing the substrate in an inert environment and by raising the temperature surrounding the substrate.

Abstract: A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C.

Abstract: A reaction chamber of the type used to create a reaction at a surface of a substrate disposed within the reaction chamber. A transmitter produces a transmitted beam having first characteristics, where the transmitter is disposed outside of the reaction chamber. A view port is disposed in a boundary wall of the reaction chamber, where the view port is formed of a material that is transparent at least in part to the transmitted beam. The transmitter, the view port, and the substrate are aligned such that the transmitted beam is directable to and reflected at least in part from the surface of the substrate, thereby producing a reflected beam having second characteristics. A receiver is disposed outside of the reaction chamber, and the receiver receives the reflected beam from the surface of the substrate through the view port. The receiver also senses the second characteristics of the reflected beam and reports the second characteristics.

Abstract: A capping layer of an insulator such as silicon nitride is formed over horizontally closely spaced apart metal lines on an oxide layer of an integrated circuit structure formed on a semiconductor substrate. Low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between the closely spaced apart metal lines is then deposited over and between the metal lines and over the silicon nitride caps on the metal lines. After the formation of such low k silicon oxide dielectric material between the closely spaced apart metal lines and the over silicon nitride caps thereon, a second layer of silicon nitride is deposited over the layer of low k silicon oxide dielectric material.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A process is described for planarizing an isolation structure in a substrate. The process includes depositing a pad protective material over an upper surface of the substrate, and selectively removing portions of the pad protective material to expose portions of the substrate and to form sidewalls in the pad protective material. A trench is formed in the exposed portions of the substrate, and a trench fill material is deposited in the trench and over the pad protective material. A trench protective material is deposited over the trench fill material and in contact with the sidewalls of the pad protective material, such that the pad protective material and portions of the trench protective material together form a continuous protective material layer. Portions of the trench protective material and the trench fill material are selectively removed down to the level of the upper surface of the pad protective material.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A ferroelectric capacitor device and method of manufacture. A substrate supports a bottom electrode structure, with an adhesion/diffusion barrier layer sandwiched therebetween. The electrode layer includes a metal or metal alloy and an oxide of the metal or alloy. The adhesion/diffusion barrier layer is a similar oxide. Ferroelectric material is sandwiched between a top electrode. The top layer includes a metal or metal alloy and an oxide of the same; the metal or metal alloy may be the same as the bottom electrode but need not be. The metal and metal oxide electrodes may be deposited by known deposition techniques, or the metal may be deposited and the oxide formed by annealing in oxygen ambient environment.

Abstract: A capacitor for use on silicon or other substrate has a multilayer electrode structure. In a preferred embodiment, a bottom electrode situated on the substrate has a bottom layer of Pt--Rh--O.sub.x, an intermediate layer of Pt--Rh, and a top layer of Pt--Rh--O.sub.x. A ferroelectric material such as PZT (or other material) is situated on the bottom electrode. A top electrode, preferably of identical composition as the bottom electrode, is situated on the opposite side of the ferroelectric from the bottom electrode.