Abstract: An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.

Abstract: A system for use in an aerospace environment includes an array of storage drives each comprising a non-radiation-hardened drive controller, a non-radiation-hardened, non-volatile, storage medium, and a non-radiation-hardened volatile memory. The system includes a radiation-tolerant storage controller coupled to the array. The storage controller provides failure-resistant data redundancy among the storage drives of the array. The system includes a bus host that accesses the array via the storage controller. The storage controller implements security logic and a root-of-trust that provides to the bus host verification of authenticity of the radiation tolerant storage controller and the storage drives.

Abstract: A data storage system can provide low cost and optimized performance with a cartridge housing multiple separate data storage devices and each of the data storage devices being concurrently engaged by a device player. The device player may have a processor configured to analyze mechanical performance of each data storage device and data performance of data resident in each data storage device.

Abstract: An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.

Abstract: A data storage system can provide low cost and optimized performance with a cartridge housing multiple separate data storage devices and each of the data storage devices being concurrently engaged by a device player. The device player may have a processor configured to analyze mechanical performance of each data storage device and data performance of data resident in each data storage device.