Patents by Inventor Hemant V. Deshpande

Hemant V. Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Enhanced dislocation stress transistor
    Patent number: 10084087
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand S. Murthy, Hemant V. Deshpande, Daniel B. Aubertine
  • ENHANCED DISLOCATION STRESS TRANSISTOR
    Publication number: 20170222052
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Applicant: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand S. Murthy, Hemant V. Deshpande, Daniel B. Aubertine
  • Strained silicon MOS device with box layer between the source and drain regions
    Patent number: 7422950
    Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Hemant V. Deshpande, Sunit Tyagi, Mark Bohr