Patents by Inventor Hemant Vats

Hemant Vats has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories
    Patent number: 9842642
    Abstract: An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: December 12, 2017
    Assignee: Synopsys, Inc.
    Inventors: M. Sultan M. Siddiqui, Shailendra Sharad, Hemant Vats, Amit Khanuja
  • Integrated Circuit for Storing Data
    Publication number: 20160049191
    Abstract: An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 18, 2016
    Inventors: Sultan M. Siddiqui, Shailendra Sharad, Hemant Vats, Amit Khanuja