Abstract: A high-resolution digital image capturing apparatus with variable resolution capability is presented. In accordance with the present invention, the image capturing apparatus implements a motion control mechanism to incrementally move the sensor array relative to a subject. A frame of the image is captured at each incremental position. The number of frames taken is essentially limited by the distance between adjacent sensors. The frames are subsequently processed and assembled to generate a picture with improved resolution. Accordingly, the image resolution is directly related to the number of frames taken. By using the concept of fractal geometry, the number of frames required for high image resolution may be reduced thereby essentially providing a compressing technique to reduce capturing and processing time. In so doing, a digital image capturing apparatus with variable resolution capability that is inexpensive, portable, and power efficient can be achieved.

Abstract: A method and apparatus to prevent invalid data from propagating into devices connected to a PCI tristate bus is provided. The method and apparatus utilize the PCI bus control signals to monitor the bus transaction's mode (e.g., as a bus target or as a bus master), type (e.g., read, write), and status (e.g., ongoing bus transaction). Using these information, control the opening and closing of a window gate hardware to allow valid data to propagate into a device connected to the PCI tristate bus and to prevent invalid data from propagating into the device.

Abstract: A method and apparatus to prevent data from being corrupted prior to reaching the final destination is provided. The method and apparatus monitors the status of posted write transactions and transaction initiations. If it is determined that a posted write transaction is incomplete and there is a pending transaction initiation, a bus retry is requested for the pending transaction.

Abstract: The present invention is implemented in a peripheral component coupled to a peripheral component interconnect (PCI) bus. The peripheral component includes an internal device operating in an internal clock domain while the PCI bus operates in a PCI clock domain. The system of the present invention efficiently interfaces the internal device with the PCI bus. The present invention generates and couples a request for PCI bus ownership, originating from the internal device, to the PCI bus. The present invention then determines whether the PCI bus is idle or busy. Where the PCI bus is idle, a proceed signal is generated for the internal device. Where the PCI bus is busy, a do not proceed signal for the internal device is generated. Both the proceed and the do not proceed signals are synchronous to the internal clock domain. The PCI bus is acquired and a data transaction from the internal device is executed when the internal device receives the proceed signal.

Abstract: A clock doubler circuit with duty cycle control includes an exclusive-OR, a toggle flip-flop, a plurality of control bit flip-flops, a primary delay element, a plurality of secondary delay elements, and a multiplexer. The toggle flip-flop has a clock input connected to an output of the exclusive-OR, and an inverted data output connected back to a data input of the toggle flip-flop and connected forward to an input of the primary delay element. An output of the primary delay element is connected to an input of the multiplexer and to individual inputs of the plurality of secondary delay elements which in turn, have outputs connected to other inputs of the multiplexer. A plurality of control bits generated, for example, by a computer program running on a host processor, are respectively provided to data inputs of the plurality of control bit flip-flops which in turn, have data outputs connected to select inputs of the multiplexer.

Abstract: A clock switching circuit responsive to at least one clock select signal switches to a selected one of a plurality of clock signals while minimizing transients generated during the switching. The circuit includes at least one flip-flop receiving a corresponding one of the at least one clock select signal; a plurality of flip-flops individually receiving an output of a corresponding one of the at least one flip-flop, and an inverted version of a corresponding one of the clock signals; a plurality of AND gates individually receiving the output of a corresponding one of the at least one flip-flop, the output of a corresponding one of the plurality of flip-flops, and a corresponding one of the plurality of clock signals; and an OR gate receiving the outputs of the AND gates so that the selected one of the plurality of clock signals is provided at an output of the OR gate, and fed back to an inverted clock input of the at least one flip-flop.

Abstract: An apparatus and method for acquiring address and command information related to a synchronous bus transaction with at most zero hold-time over substantially the duration of the bus transaction. Due to state changes, bus transaction address and command information may become invalid over the duration of the bus transaction. A transparent latch circuit is used to make the information available as soon as the information is received and to acquire valid information related to the bus transaction before a rising clock edge of the next clock cycle following a bus transaction request. A synchronous flip-flop circuit is utilized simultaneously to capture alternate valid information related to a bus transaction having at most zero hold-time. The acquired valid information and the alternately acquired valid information ensure that stable and valid bus transaction information are available over substantially the duration of the transaction. Moreover, by decoding the information as soon as they are received (i.e.

Abstract: An apparatus and method for acquiring data information provided by a synchronous bus transaction with at most zero hold-time. A transparent latch circuit is used to capture bus transaction information before a rising clock edge of the next clock cycle following a bus transaction request and a data phase starting signal thereby meeting the zero-hold requirement. At the same time, bus transaction information is decoded to determine whether the current phase is a data phase, data information is present in the current bus transaction, memory addresses presented are within an allowable range, and bus transaction command is of the type recognized. If all the above conditions are met, the information captured by the transparent latch circuit is registered by a synchronous flip-flop circuit as valid data information.