Patents by Inventor Hemanth K. Dhavaleswarapu
Hemanth K. Dhavaleswarapu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11676873Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.Type: GrantFiled: June 30, 2017Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Dinesh Padmanabhan Ramalekshmi Thanu, Hemanth K. Dhavaleswarapu, Venkata Suresh Guthikonda, John J. Beatty, Yonghao An, Marco Aurelio Cartas Ayala, Luke J. Garner, Peng Li
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Patent number: 11652018Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.Type: GrantFiled: June 9, 2021Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
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Publication number: 20210305118Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.Type: ApplicationFiled: June 9, 2021Publication date: September 30, 2021Applicant: Intel CorporationInventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
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Patent number: 11062970Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.Type: GrantFiled: August 29, 2017Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
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Publication number: 20200185290Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.Type: ApplicationFiled: June 30, 2017Publication date: June 11, 2020Inventors: Dinesh PADMANABHAN RAMALEKSHMI THANU, Hemanth K. DHAVALESWARAPU, Venkata Suresh GUTHIKONDA, John J. BEATTY, Yonghao AN, Marco Aurelio CARTAS AYALA, Luke J. GARNER, Peng LI
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Patent number: 10643938Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, a plurality of microelectronic devices attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one of the plurality of microelectronic devices and attached to the microelectronic substrate, and at least one offset spacer attached between the microelectronic substrate and the heat dissipation device to control the bondline thickness between the heat dissipation device and at least one of the plurality of microelectronic devices.Type: GrantFiled: May 31, 2017Date of Patent: May 5, 2020Assignee: Intel CorporationInventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Sachin Deshmukh
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Patent number: 10580717Abstract: A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.Type: GrantFiled: January 11, 2016Date of Patent: March 3, 2020Assignee: Intel CorporationInventors: Boxi Liu, Hemanth K. Dhavaleswarapu, Syadwad Jain, James C. Matayabas, Jr.
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Publication number: 20190067153Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: Intel CorporationInventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
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Publication number: 20180374776Abstract: A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.Type: ApplicationFiled: January 11, 2016Publication date: December 27, 2018Inventors: Boxi LIU, Hemanth K. DHAVALESWARAPU, Syadwad JAIN, James C. MATAYABAS, Jr.
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Publication number: 20180350712Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, a plurality of microelectronic devices attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one of the plurality of microelectronic devices and attached to the microelectronic substrate, and at least one offset spacer attached between the microelectronic substrate and the heat dissipation device to control the bondline thickness between the heat dissipation device and at least one of the plurality of microelectronic devices.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Applicant: INTEL CORPORATIONInventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Sachin Deshmukh
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Patent number: 9943931Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.Type: GrantFiled: July 27, 2016Date of Patent: April 17, 2018Assignee: Intel CorporationInventors: Zhihua Li, Hemanth K. Dhavaleswarapu, Joseph B. Petrini, Shankar Devasenathipathy, Steven B. Roach, Ioan Sauciuc, Pranav K. Desai, George S. Kostiew, Sanjoy K. Saha
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Patent number: 9735089Abstract: Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.Type: GrantFiled: September 24, 2015Date of Patent: August 15, 2017Assignee: Intel CorporationInventors: Siddarth Kumar, Hemanth K. Dhavaleswarapu
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Publication number: 20170092564Abstract: Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: September 24, 2015Publication date: March 30, 2017Applicant: Intel CorporationInventors: Siddarth Kumar, Hemanth K. Dhavaleswarapu
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Publication number: 20170014957Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.Type: ApplicationFiled: July 27, 2016Publication date: January 19, 2017Applicant: Intel CorporationInventors: Zhihua Li, Hemanth K. Dhavaleswarapu, Joseph B. Petrini, Shankar Devasenathipathy, Steven B. Roach, Ioan Sauciuc, Pranav K. Desai, George S. Kostiew, Sanjoy K. Saha
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Patent number: 9434029Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.Type: GrantFiled: December 20, 2011Date of Patent: September 6, 2016Assignee: Intel CorporationInventors: Zhihua Li, Hemanth K. Dhavaleswarapu, Joseph B. Petrini, Shankar Devasenathipathy, Steven B. Roach, Ioan Sauciuc, Pranav K. Desai, George S. Kostiew, Sanjoy K. Saha
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Publication number: 20150170989Abstract: Embodiments of the present disclosure describe thermal management solutions for multichip package assemblies and methods of fabricating multichip package assemblies utilizing the thermal management solutions. These embodiments include multi-level heat spreaders and alleviate issues caused by dimensional variability in die-packages utilized in multichip package assemblies. In one embodiment a package heat spreader is thermally coupled to a first die-package and die-package heat spreader. The die-package heat spreader is thermally coupled to a second die-package and provides a thermal pathway to conduct heat from the second die-package to the package heat spreader. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 16, 2013Publication date: June 18, 2015Inventors: Hemanth K. Dhavaleswarapu, Roger D. Flynn, Sanjoy K. Saha
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Publication number: 20130299133Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.Type: ApplicationFiled: December 20, 2011Publication date: November 14, 2013Inventors: Zhihua Li, Hemanth K. Dhavaleswarapu, Joseph B. Petrini, Shankar Devasenathipathy, Steven B. Roach, Ioan Sauciuc, Pranav K. Desai, George S. Kostiew, Sanjoy K. Saha