Patents by Inventor Hemanth K. Dhavaleswarapu

Hemanth K. Dhavaleswarapu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11676873
    Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Dinesh Padmanabhan Ramalekshmi Thanu, Hemanth K. Dhavaleswarapu, Venkata Suresh Guthikonda, John J. Beatty, Yonghao An, Marco Aurelio Cartas Ayala, Luke J. Garner, Peng Li
  • Patent number: 11652018
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Publication number: 20210305118
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Patent number: 11062970
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Publication number: 20200185290
    Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.
    Type: Application
    Filed: June 30, 2017
    Publication date: June 11, 2020
    Inventors: Dinesh PADMANABHAN RAMALEKSHMI THANU, Hemanth K. DHAVALESWARAPU, Venkata Suresh GUTHIKONDA, John J. BEATTY, Yonghao AN, Marco Aurelio CARTAS AYALA, Luke J. GARNER, Peng LI
  • Patent number: 10643938
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, a plurality of microelectronic devices attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one of the plurality of microelectronic devices and attached to the microelectronic substrate, and at least one offset spacer attached between the microelectronic substrate and the heat dissipation device to control the bondline thickness between the heat dissipation device and at least one of the plurality of microelectronic devices.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Sachin Deshmukh
  • Patent number: 10580717
    Abstract: A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Boxi Liu, Hemanth K. Dhavaleswarapu, Syadwad Jain, James C. Matayabas, Jr.
  • Publication number: 20190067153
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Applicant: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Publication number: 20180374776
    Abstract: A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.
    Type: Application
    Filed: January 11, 2016
    Publication date: December 27, 2018
    Inventors: Boxi LIU, Hemanth K. DHAVALESWARAPU, Syadwad JAIN, James C. MATAYABAS, Jr.
  • Publication number: 20180350712
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, a plurality of microelectronic devices attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one of the plurality of microelectronic devices and attached to the microelectronic substrate, and at least one offset spacer attached between the microelectronic substrate and the heat dissipation device to control the bondline thickness between the heat dissipation device and at least one of the plurality of microelectronic devices.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Applicant: INTEL CORPORATION
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Sachin Deshmukh
  • Patent number: 9943931
    Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: April 17, 2018
    Assignee: Intel Corporation
    Inventors: Zhihua Li, Hemanth K. Dhavaleswarapu, Joseph B. Petrini, Shankar Devasenathipathy, Steven B. Roach, Ioan Sauciuc, Pranav K. Desai, George S. Kostiew, Sanjoy K. Saha
  • Patent number: 9735089
    Abstract: Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Siddarth Kumar, Hemanth K. Dhavaleswarapu
  • Publication number: 20170092564
    Abstract: Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: September 24, 2015
    Publication date: March 30, 2017
    Applicant: Intel Corporation
    Inventors: Siddarth Kumar, Hemanth K. Dhavaleswarapu
  • Publication number: 20170014957
    Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.
    Type: Application
    Filed: July 27, 2016
    Publication date: January 19, 2017
    Applicant: Intel Corporation
    Inventors: Zhihua Li, Hemanth K. Dhavaleswarapu, Joseph B. Petrini, Shankar Devasenathipathy, Steven B. Roach, Ioan Sauciuc, Pranav K. Desai, George S. Kostiew, Sanjoy K. Saha
  • Patent number: 9434029
    Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Zhihua Li, Hemanth K. Dhavaleswarapu, Joseph B. Petrini, Shankar Devasenathipathy, Steven B. Roach, Ioan Sauciuc, Pranav K. Desai, George S. Kostiew, Sanjoy K. Saha
  • Publication number: 20150170989
    Abstract: Embodiments of the present disclosure describe thermal management solutions for multichip package assemblies and methods of fabricating multichip package assemblies utilizing the thermal management solutions. These embodiments include multi-level heat spreaders and alleviate issues caused by dimensional variability in die-packages utilized in multichip package assemblies. In one embodiment a package heat spreader is thermally coupled to a first die-package and die-package heat spreader. The die-package heat spreader is thermally coupled to a second die-package and provides a thermal pathway to conduct heat from the second die-package to the package heat spreader. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Inventors: Hemanth K. Dhavaleswarapu, Roger D. Flynn, Sanjoy K. Saha
  • Publication number: 20130299133
    Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.
    Type: Application
    Filed: December 20, 2011
    Publication date: November 14, 2013
    Inventors: Zhihua Li, Hemanth K. Dhavaleswarapu, Joseph B. Petrini, Shankar Devasenathipathy, Steven B. Roach, Ioan Sauciuc, Pranav K. Desai, George S. Kostiew, Sanjoy K. Saha