Abstract: A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the GNSS receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the GNSS receiver processor. An optional ancillary memory system can provide additional memory to the general processor when the GNSS receiver processor has allocated memory that the general processor would otherwise use.

Abstract: An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit (320) operable to coherently integrate the correlation results over plural sample windows (PreD1, PreD2) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD1, PreD2) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.

Abstract: A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the GNSS receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the GNSS receiver processor. An optional ancillary memory system can provide additional memory to the general processor when the GNSS receiver processor has allocated memory that the general processor would otherwise use.

Abstract: An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit (320) operable to coherently integrate the correlation results over plural sample windows (PreD1, PreD2) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD1, PreD2) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.

Abstract: An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit (320) operable to coherently integrate the correlation results over plural sample windows (PreD1, PreD2) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD1, PreD2) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.

Abstract: An integrated circuit for facilitating spread spectrum reception of data having a data bit period includes an hypothesis search circuit (120, 210, 220) operable to correlate a pseudorandom code with a signal input based on a received signal to produce correlation results, and a processor circuit (320) operable to coherently integrate the correlation results over plural sample windows (PreD1, PreD2) staggered relative to each other in the coherent integration interval and to non-coherently combine the coherently integrated results corresponding to the plural sample windows (PreD1, PreD2) to produce a received signal output, whereby enhancing performance. Other circuits, receivers and processes are also disclosed.