Abstract: A hardware architecture for a universal testing system used for performing tests on cable modem devices (DUT) is disclosed. According to certain embodiments, a CMTS test harness enables the DUT to respond to test phone calls from the MOCA interface and which test phone calls terminate at the DUT's phone port.

Abstract: A hardware architecture for a universal testing system used for performing tests on cable modem devices (DUT) is disclosed. According to certain embodiments, a CMTS test harness enables the DUT to respond to test phone calls from the MOCA interface and which test phone calls terminate at the DUT's phone port.

Abstract: A hardware architecture for a universal testing system used for performing Wifi tests on wireless devices under test (DUT) is disclosed. According to certain embodiments, test information travels from a Wifi port of the test server to the Wifi port's antenna in a Faraday cage, and then travels over the air to DUT's Wifi antenna in the same Faraday cage, and then to a LAN Ethernet port of the DUT, and then to the test server's Ethernet port.

Abstract: A hardware architecture for a universal testing system used for performing tests on cable modem devices (OUT) is disclosed. According to certain embodiments, a CMTS test harness enables the DUT to respond to test phone calls from the MOCA interface and which test phone calls terminate at the DUT's phone port.

Abstract: A hardware architecture for a universal testing system used for performing Wfi tests on wireless devices under test (DUT) is disclosed. According to certain embodiments, test information travels from a Wifi port of the test server to the Wifi port's antenna in a Faraday cage, and then travels over the air to DUT's Wifi antenna in the same Faraday cage, and then to a LAN Ethernet port of the DUT, and then to the test server's Ethernet port.

Abstract: A universal testing system platform with a modular and symmetrical design that provides faraday cages in a flexible, efficient and space saving architecture for testing wireless devices.

Abstract: A hardware architecture for a universal testing system used for performing Wifi tests on wireless devices under test (DUT) is disclosed. According to certain embodiments, test information travels from a Wifi port of the test server to the Wifi port's antenna in a Faraday cage, and then travels over the air to DUT's Wifi antenna in the same Faraday cage, and then to a LAN Ethernet port of the DUT, and then to the test server's Ethernet port.

Abstract: A universal testing system platform with a modular and symmetrical design that provides a flexible, efficient and space saving architecture for testing wireless devices is disclosed.

Abstract: A universal testing system platform with a modular and symmetrical design that provides a flexible, efficient and space saving architecture for testing wireless devices is disclosed.

Abstract: A hardware architecture for a universal testing system used for performing Wifi tests on wireless devices under test (DUT) is disclosed. According to certain embodiments, test information travels from a Wifi port of the test server to the Wifi port's antenna in a Faraday cage, and then travels over the air to DUT's Wifi antenna in the same Faraday cage, and then to a LAN Ethernet port of the DUT, and then to the test server's Ethernet port.

Abstract: A hardware architecture for a universal testing system used for performing tests on cable modem devices (DUT) is disclosed. According to certain embodiments, a CMTS test harness enables the DUT to respond to test phone calls from the MOCA interface and which test phone calls terminate at the DUT's phone port.

Abstract: A system and method for global power management in a power over Ethernet (PoE) chassis. Power supply status signals indicative of an operating condition of a plurality of power supplies are provided to a plurality of power sourcing equipment (PSE) controller chips in a plurality of blades of a chassis system. Pre-configured combination logic within each of the PSE controller chips converts an indicated operational state of the plurality of power supplies into a powering decision for each of the ports served by the PSE controller chip. Global power management is also effected through the use of scaling factors for the various blades to ensure that the lowest priority powered port (LPPP) in a first blade does not have a lower priority than the highest priority non-powered port (HPNPP) in a second blade.

Abstract: A system and method for power sourcing equipment (PSE) detection of a powered device (PD) power failure for power backup. A PSE can power a PD at a low level of power as a backup power source. Upon a failure in the PDs primary power source, the PSE can detect a transient (e.g., current and/or voltage) on the PD load as a signal that the PD requires additional power. The PSE can then allocate increased power to the port by entering into an active state as compared to a backup state. As the PSE is responsive to the detection of the transient, the PSE need not rely on a real-time communication from the PD.

Abstract: A power over Ethernet (PoE) power sourcing equipment (PSE) architecture for variable maximum power delivery. PoE PSE subsystems rely on some control to “turn on” a power field effect transistor (FET), which allows current to be transmitted to a powered device (PD). A hybrid approach is provided where an internal FET can be augmented with an external FET to provide an architecture that can be flexibly applied to applications with various space, cost and cooling limitations. The maximum delivered power can also be boosted with the addition of an external FET to the internal FET.

Abstract: A system and method for automatically discovering total transistor resistance in a hybrid power over Ethernet (PoE) architecture. A critical factor for a PoE system is the total resistance of the power FET. Typical PoE systems consist of a single power FET that may be integrated with the controller or external to the controller. In a hybrid architecture the PoE system consists of both an internal power FET and an external power FET. The external power FET can be used to customize a design to meet a particular application or need. The total resistance in the hybrid architecture can be automatically determined using voltage and current measurements of the internal and external power FETs.

Abstract: A power over Ethernet (PoE) power sourcing equipment (PSE) architecture for variable maximum power delivery. PoE PSE subsystems rely on some control to “turn on” a power field effect transistor (FET), which allows current to be transmitted to a powered device (PD). A hybrid approach is provided where an internal FET can be augmented with an external FET to provide an architecture that can be flexibly applied to applications with various space, cost and cooling limitations. The maximum delivered power can also be boosted with the addition of an external FET to the internal FET.

Abstract: A system and method for global power management in a power over Ethernet (PoE) chassis. Power supply status signals indicative of an operating condition of a plurality of power supplies are provided to a plurality of power sourcing equipment (PSE) controller chips in a plurality of blades of a chassis system. Pre-configured combination logic within each of the PSE controller chips converts an indicated operational state of the plurality of power supplies into a powering decision for each of the ports served by the PSE controller chip. Global power management is also effected through the use of scaling factors for the various blades to ensure that the lowest priority powered port (LPPP) in a first blade does not have a lower priority than the highest priority non-powered port (HPNPP) in a second blade.

Abstract: A power over Ethernet (PoE) power sourcing equipment (PSE) architecture for variable maximum power delivery. PoE PSE subsystems rely on some control to “turn on” a power field effect transistor (FET), which allows current to be transmitted to a powered device (PD). A hybrid approach is provided where an internal FET can be augmented with an external FET to provide an architecture that can be flexibly applied to applications with various space, cost and cooling limitations. The maximum delivered power can also be boosted with the addition of an external FET to the internal FET.

Abstract: A system and method for power sourcing equipment (PSE) detection of a powered device (PD) power failure for power backup. A PSE can power a PD at a low level of power as a backup power source. Upon a failure in the PDs primary power source, the PSE can detect a transient (e.g., current and/or voltage) on the PD load as a signal that the PD requires additional power. The PSE can then allocate increased power to the port by entering into an active state as compared to a backup state. As the PSE is responsive to the detection of the transient, the PSE need not rely on a real-time communication from the PD.

Abstract: A system and method for automatically discovering total transistor resistance in a hybrid power over Ethernet (PoE) architecture. A critical factor for a PoE system is the total resistance of the power FET. Typical PoE systems consist of a single power FET that may be integrated with the controller or external to the controller. In a hybrid architecture the PoE system consists of both an internal power FET and an external power FET. The external power FET can be used to customize a design to meet a particular application or need. The total resistance in the hybrid architecture can be automatically determined using voltage and current measurements of the internal and external power FETs.