Abstract: A circuit and method are described for generating a low jitter output clock having an arbitrary non-integer divide ratio relative to a high-frequency clock. Integer divide ratios of the high-frequency clock may be achieved by dividing the high-frequency clock by the reference clock and phase locking the output clock to the high-frequency clock. Non-integer divide ratios can be achieved by dividing the high-frequency clock by the nearest integer, rounded down, and then delaying the resultant output clock by the modulus of the division. The delay can then be rotated across to create a clock with a non-integer divide ratio relative to the high-frequency clock. By doing so, a high-frequency clock may be used that is not constrained by having a frequency that is an integer multiple of each desired component-specific output clock signal.

Abstract: A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

Abstract: A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

Abstract: A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

Abstract: A circuit and method for storing bit values in capacitors of a set-reset latch of a dynamic comparator are described. A capacitor-based SR latch architecture is disclosed that makes use of the parasitic capacitances present at its output to store a digital bit value. During the comparator's sampling phase, the capacitor-based SR latch behaves as an inverter and buffers the sampled value to the output of the SR latch. In doing so, it charges the parasitic capacitors associated with the routing and downstream circuitry up or down. When the dynamic comparator enters the reset phase, the SR latch turns off and makes use of the of the parasitic capacitors to hold the previously-buffered value.

Abstract: A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

Abstract: A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

Abstract: Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal.

Abstract: Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal.

Abstract: An optical receiver includes a photodetector for detecting incoming optical data signals and an amplifier for providing signal gain and current to voltage conversion. The detection signal generated by the photodetector may include a distortion component caused by an operating characteristic of the photodetector. A signal compensating circuit may reconstruct the received optical data signal by effectively canceling the distortion component. For this purpose, the signal compensating circuit may include a decision feedback equalizer implemented using at least one feedback filter matched to the operating characteristic of the photodetector causing the signal distortion so as to reproduce the distortion component for cancellation. Use of a control module may also configure the optical receiver in real time to account for other operating and environmental conditions of the optical receiver.

Abstract: An optical receiver includes a photodetector for detecting incoming optical data signals and an amplifier for providing signal gain and current to voltage conversion. The detection signal generated by the photodetector may include a distortion component caused by an operating characteristic of the photodetector. A signal compensating circuit may reconstruct the received optical data signal by effectively canceling the distortion component. For this purpose, the signal compensating circuit may include a decision feedback equalizer implemented using at least one feedback filter matched to the operating characteristic of the photodetector causing the signal distortion so as to reproduce the distortion component for cancellation. Use of a control module may also configure the optical receiver in real time to account for other operating and environmental conditions of the optical receiver.