Patents by Inventor Hemlata Gupta
Hemlata Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250005244Abstract: Timing constraint auto-creation for integrated circuit testing includes analyzing an integrated circuit design using a first clocking attribute, wherein the first clocking attribute describes a first clock for the integrated circuit design; identifying, based on the analysis and the first clocking attribute, design features of the integrated circuit design necessitating timing constraints; and generating, based on the identified design features, the timing constraints for the static timing analysis of the integrated circuit design.Type: ApplicationFiled: June 27, 2023Publication date: January 2, 2025Inventors: ERIC FOREMAN, JACK DILULLO, NATHAN BUCK, MICHAEL HEMSLEY WOOD, ROBERT JOHN ALLEN, HEMLATA GUPTA, NATESAN VENKATESWARAN, KERIM KALAFALA
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Publication number: 20240386175Abstract: The present disclosure describes systems and methods for performing timing analysis of circuit designs. According to an embodiment, a method includes assigning a timing margin to a non-scan latch of a circuit design and performing a timing analysis on the circuit design using the timing margin for the non-scan latch to produce timing results for the circuit design. The timing results include a slack value. The method also includes calculating a credit based on the slack value and updating the slack value based on the credit.Type: ApplicationFiled: May 18, 2023Publication date: November 21, 2024Inventors: Kerim KALAFALA, Michael Hemsley WOOD, Rahul M. RAO, Tsz-Mei KO, Daniel DEDRICK, Eric FOREMAN, Robert John ALLEN, Nathan BUCK, Hemlata GUPTA, Karthik RAJASHEKARA
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Publication number: 20240330551Abstract: Timing analysis of a digital integrated circuit using intent based timing constraints includes defining a plurality of intent groups for an integrated circuit design. Each intent group is associated with a different clock type of the integrated circuit design. A different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design is associated with each intent group. One or more timing constraints is associated with each of the intent groups. A timing result is computed based on propagating the timing phases of each of the intent groups and applying the associated timing constraints from an input to a timing point of the integrated circuit design.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Inventors: HEMLATA GUPTA, KERIM KALAFALA, MANISH VERMA, JENNIFER ELIZABETH BASILE, ADIL BHANJI, ERIC FOREMAN, JACK DILULLO
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Publication number: 20240330556Abstract: Timing analysis of a digital integrated circuit includes determining an initial delay value for a gate of an integrated circuit design. The gate is located within a predefined area of the integrated circuit design. A first scale factor is calculated based on a number of switching transistors within the predefined area, and a second scale factor is calculated based on a voltage drop value associated with the predefined area. An updated delay value for the gate is calculated based on the initial delay value, the first scale factor, and the second scale factor.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Inventors: JAMES J. ENGEL, JENNIFER ELIZABETH BASILE, HEMLATA GUPTA, MICHAEL HEMSLEY WOOD, KERIM KALAFALA, VASANT RAO, ALEXANDER JOEL SUESS
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Patent number: 10902167Abstract: To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.Type: GrantFiled: July 9, 2019Date of Patent: January 26, 2021Assignee: International Business Machines CorporationInventors: Chaitanya Ravindra Peddawad, Kerim Kalafala, Alexander Joel Suess, Hemlata Gupta, Gregory Schaeffer
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Publication number: 20210011980Abstract: To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.Type: ApplicationFiled: July 9, 2019Publication date: January 14, 2021Inventors: Chaitanya Ravindra Peddawad, Kerim Kalafala, Alexander Joel Suess, Hemlata Gupta, Gregory Schaeffer
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Publication number: 20190362043Abstract: A system and method involves partitioning a design of an integrated circuit into two or more hierarchical levels. A lowest level includes macros and a higher level includes some or all of the macros. Each of the macros includes two or more components. A macro timing model corresponding with each of the macros indicates a delay through the macro. The macro timing model corresponding with ones of the macros that are part of the higher level are loaded to perform higher-level timing analysis, which indicates a delay through the ones of the macros that are part of the higher level. Modified macro timing models corresponding with one or more of the macros are generated, and only the modified macro timing models associated with the macros that are part of the higher level modify corresponding loaded macro timing models to continue the higher-level timing analysis.Type: ApplicationFiled: May 24, 2018Publication date: November 28, 2019Inventors: Hemlata Gupta, Alexander Suess, Adil Bhanji, Nathan Buck, Michel P. Robert, Edward Hughes, Kerim Kalafala, Jennifer E. Basile, Jack DiLullo, Adam Matheny, Michael H. Wood
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Patent number: 10354046Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.Type: GrantFiled: November 13, 2017Date of Patent: July 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
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Patent number: 10169527Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.Type: GrantFiled: November 15, 2017Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hemlata Gupta, Debjit Sinha, Chandramouli Visweswariah
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Patent number: 10169503Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: GrantFiled: February 15, 2018Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Publication number: 20180173833Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Patent number: 9985843Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.Type: GrantFiled: February 27, 2015Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
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Patent number: 9977850Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: GrantFiled: July 12, 2016Date of Patent: May 22, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Patent number: 9940431Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.Type: GrantFiled: January 7, 2016Date of Patent: April 10, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hemlata Gupta, Debjit Sinha, Chandramouli Visweswariah
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Publication number: 20180075183Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.Type: ApplicationFiled: November 15, 2017Publication date: March 15, 2018Inventors: Hemlata Gupta, Debjit Sinha, Chandramouli Visweswariah
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Publication number: 20180068051Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.Type: ApplicationFiled: November 13, 2017Publication date: March 8, 2018Inventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
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Patent number: 9910954Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.Type: GrantFiled: May 26, 2016Date of Patent: March 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
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Publication number: 20180018421Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
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Patent number: 9853866Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.Type: GrantFiled: January 10, 2017Date of Patent: December 26, 2017Assignee: International Business Machines CorporationInventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
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Publication number: 20170344693Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.Type: ApplicationFiled: May 26, 2016Publication date: November 30, 2017Inventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood