Patents by Inventor Hemlata Gupta

Hemlata Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250005244
    Abstract: Timing constraint auto-creation for integrated circuit testing includes analyzing an integrated circuit design using a first clocking attribute, wherein the first clocking attribute describes a first clock for the integrated circuit design; identifying, based on the analysis and the first clocking attribute, design features of the integrated circuit design necessitating timing constraints; and generating, based on the identified design features, the timing constraints for the static timing analysis of the integrated circuit design.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Inventors: ERIC FOREMAN, JACK DILULLO, NATHAN BUCK, MICHAEL HEMSLEY WOOD, ROBERT JOHN ALLEN, HEMLATA GUPTA, NATESAN VENKATESWARAN, KERIM KALAFALA
  • Publication number: 20240386175
    Abstract: The present disclosure describes systems and methods for performing timing analysis of circuit designs. According to an embodiment, a method includes assigning a timing margin to a non-scan latch of a circuit design and performing a timing analysis on the circuit design using the timing margin for the non-scan latch to produce timing results for the circuit design. The timing results include a slack value. The method also includes calculating a credit based on the slack value and updating the slack value based on the credit.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Inventors: Kerim KALAFALA, Michael Hemsley WOOD, Rahul M. RAO, Tsz-Mei KO, Daniel DEDRICK, Eric FOREMAN, Robert John ALLEN, Nathan BUCK, Hemlata GUPTA, Karthik RAJASHEKARA
  • Publication number: 20240330551
    Abstract: Timing analysis of a digital integrated circuit using intent based timing constraints includes defining a plurality of intent groups for an integrated circuit design. Each intent group is associated with a different clock type of the integrated circuit design. A different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design is associated with each intent group. One or more timing constraints is associated with each of the intent groups. A timing result is computed based on propagating the timing phases of each of the intent groups and applying the associated timing constraints from an input to a timing point of the integrated circuit design.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: HEMLATA GUPTA, KERIM KALAFALA, MANISH VERMA, JENNIFER ELIZABETH BASILE, ADIL BHANJI, ERIC FOREMAN, JACK DILULLO
  • Publication number: 20240330556
    Abstract: Timing analysis of a digital integrated circuit includes determining an initial delay value for a gate of an integrated circuit design. The gate is located within a predefined area of the integrated circuit design. A first scale factor is calculated based on a number of switching transistors within the predefined area, and a second scale factor is calculated based on a voltage drop value associated with the predefined area. An updated delay value for the gate is calculated based on the initial delay value, the first scale factor, and the second scale factor.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: JAMES J. ENGEL, JENNIFER ELIZABETH BASILE, HEMLATA GUPTA, MICHAEL HEMSLEY WOOD, KERIM KALAFALA, VASANT RAO, ALEXANDER JOEL SUESS
  • Patent number: 10902167
    Abstract: To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chaitanya Ravindra Peddawad, Kerim Kalafala, Alexander Joel Suess, Hemlata Gupta, Gregory Schaeffer
  • Publication number: 20210011980
    Abstract: To increase the efficiency of electronic design automation, in a putative electronic logic circuit design, at least one transparent latch is identified as a candidate for slack stealing. An initial timing slack, available for stealing, and associated with the at least one transparent latch, is determined. Responsive to a determination that the initial timing slack available for stealing is insufficient, it is determined whether the initial timing slack available for stealing is on a feedback path. If so, responsive to determining that the initial timing slack available for stealing is on the feedback path, the initial timing slack available for stealing is replaced with a next worse slack.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 14, 2021
    Inventors: Chaitanya Ravindra Peddawad, Kerim Kalafala, Alexander Joel Suess, Hemlata Gupta, Gregory Schaeffer
  • Publication number: 20190362043
    Abstract: A system and method involves partitioning a design of an integrated circuit into two or more hierarchical levels. A lowest level includes macros and a higher level includes some or all of the macros. Each of the macros includes two or more components. A macro timing model corresponding with each of the macros indicates a delay through the macro. The macro timing model corresponding with ones of the macros that are part of the higher level are loaded to perform higher-level timing analysis, which indicates a delay through the ones of the macros that are part of the higher level. Modified macro timing models corresponding with one or more of the macros are generated, and only the modified macro timing models associated with the macros that are part of the higher level modify corresponding loaded macro timing models to continue the higher-level timing analysis.
    Type: Application
    Filed: May 24, 2018
    Publication date: November 28, 2019
    Inventors: Hemlata Gupta, Alexander Suess, Adil Bhanji, Nathan Buck, Michel P. Robert, Edward Hughes, Kerim Kalafala, Jennifer E. Basile, Jack DiLullo, Adam Matheny, Michael H. Wood
  • Patent number: 10354046
    Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
  • Patent number: 10169527
    Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemlata Gupta, Debjit Sinha, Chandramouli Visweswariah
  • Patent number: 10169503
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Publication number: 20180173833
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Patent number: 9985843
    Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
  • Patent number: 9977850
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Patent number: 9940431
    Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemlata Gupta, Debjit Sinha, Chandramouli Visweswariah
  • Publication number: 20180075183
    Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Inventors: Hemlata Gupta, Debjit Sinha, Chandramouli Visweswariah
  • Publication number: 20180068051
    Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 8, 2018
    Inventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
  • Patent number: 9910954
    Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: March 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood
  • Publication number: 20180018421
    Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
    Type: Application
    Filed: July 12, 2016
    Publication date: January 18, 2018
    Inventors: Naiju K. Abdul, Adil Bhanji, Hemlata Gupta, Kerim Kalafala, Alex Rubin, Manish Verma
  • Patent number: 9853866
    Abstract: According to one exemplary embodiment, a method for parallel processing a network of nodes having at least one ordering constraint and at least one conflict constraint is provided. The method may include breaking a plurality of loops caused by the at least one ordering constraint. The method may also include determining a node order based on the at least one ordering constraint. The method may then include determining a conflict order based on the at least one conflict constraint, whereby no new loops are created in the network. The method may further include performing parallel processing of the network of nodes based on the node order and the conflict order.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Ronald D. Rose
  • Publication number: 20170344693
    Abstract: A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for a timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.
    Type: Application
    Filed: May 26, 2016
    Publication date: November 30, 2017
    Inventors: Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen, Stephen G. Shuma, Manish Verma, James D. Warnock, Michael H. Wood