Abstract: An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by incorporating the series of inverters in a ring oscillator.

Abstract: A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.

Abstract: A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.

Abstract: An integrated circuit comprises a plurality of sensing circuits (12), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register (11) for shifting digital data signals that represent the respective reference values from a successive approximation update circuit (14) to the sensing circuits (12) and back to the successive approximation update circuit (14). Detection results of the sensing circuits (12) are shifted to the successive approximation update circuit (14) with the digital data signals. The successive approximation update circuit (14) is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit (14) is shared by a plurality of sensing circuits (12).

Abstract: An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by in corporating the series of inverters in a ring oscillator.

Abstract: An integrated circuit (1) comprises a monitor (M1, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (M1, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SR1, SR2, SR3) and is operable to output monitor data through the shift register (SR1, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.

Abstract: An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103), each of the functional blocks (101, 102, 103) being coupled between a first power supply line (110) and a second power supply line (120). A first functional block (101) is coupled to the first power supply line (110) via a first conductive path including a first switch (131) and a second functional block (102) is coupled to the first power supply line (110) via a second conductive path including a second switch (132), the first switch (131) and the second switch (132) being arranged to respectively disconnect the first functional block (101) and the second functional block (102) from the first power supply line (110) for switching said functional blocks (101, 102) from an active mode to a standby mode.

Abstract: An electronic circuit comprises clocked functional circuits which receive a clock signal via a clock switch. The clock switch contains an enabled non-inverting driver which switches a connection between a power supply input and a clock output on and off under control of a clock signal only when the clock switch is enabled by an enable signal. The clock switch also contains a transmission switch coupled between a clock input and the clock output. The transmission switch is controlled from the enable input and makes a conductive connection between the clock input and the clock output only when the clock switch is enabled by the enable signal. As a result, transitions in the clock signal reach the functional circuits with less delay and power take-up needed to drive the clock signal is distributed so that there is less supply bounce.