Patents by Inventor Hendricus Joseph Veendrick

Hendricus Joseph Veendrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7791357
    Abstract: The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50).
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventors: Praveen Pavithran, Marcel Pelgrom, Jean Wieling, Hendricus Joseph Veendrick
  • Publication number: 20080191732
    Abstract: An integrated circuit is provided with a distributed supply voltage monitoring system in which a single controller controls a plurality of voltage monitors located in respective modules of the integrated circuit. The controller and each circuit form a successive approximation analogue to digital converter Such a system enables a small size monitoring circuit to be realized for every module of the integrated circuit.
    Type: Application
    Filed: April 20, 2006
    Publication date: August 14, 2008
    Applicant: NXP B.V.
    Inventors: Marcel Pelgrom, Violeta Petrescu, Hendricus Joseph Veendrick
  • Publication number: 20080143348
    Abstract: The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50).
    Type: Application
    Filed: December 19, 2005
    Publication date: June 19, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Praveen Pavithran, Marcel Pelgrom, Jean Wieling, Hendricus Joseph Veendrick