Abstract: A phase-looked loop circuit with holdover mode is formed utilizing a primary and secondary phase-locked loop circuits. Each loop circuit comprises a phase detector, loop filter, VCXO and frequency divider. The secondary loop is configured such that its output is very stable. The primary loop is phase-locked on a received reference clock signal and the second loop is phase locked on the output of the primary loop. The scaled output of the secondary loop being parallel to the reference clock signal. If the incoming reference signal is interrupted or lost the circuit is switched to a holdover mode where the input of the primary loop is switched to the stable scaled output of the secondary loop. In holdover mode, the output of the primary loop is phase-looked to the stable output of the secondary loop. When the reference clock signal is reestablished, the input of the primary loop is switched back to the reference clock signal.

Abstract: A phase-locked loop circuit which utilizes multiple reference signals is formed with control circuitry to minimize time interval error. The phase-locked loop (PLL) comprises a switching device, phase detector, loop filter governable oscillator, frequency divider, signal sensing circuit and a TIE reduction control circuit. The PLL maintains a substantially constant .pi./2 radians between a first reference signal and its phase-locked output. Upon loss of the first reference signal, the signal sensing circuit causes the switching device to switch to a second reference signal. The second reference signal is of the same frequency but unknown phase relationship with the interrupted first reference signal. Upon switch over, the TIE reduction control circuit causes the frequency divider output to be interrupted and forced high for a quarter-cycle of the period of the reference signals to force the PLL to phase-lock on the second reference signal with minimal TIE.

Abstract: A frame aligner circuit for aligning a plurality of information packet signals received within a maximum starting time variation interval consists of a plurality of frame detectors, stretch circuits and variable delay circuits which are controlled by a synchronization signal generator and a delay control circuit. The delay control circuit in one embodiment of the present invention delays each information packet signal for a duration of time defined by the start of the information packet signal and an interval of time following the start of a last received information packet signals. In this manner, each information packet signal is delayed a corresponding period of time to align the plurality of information packet signals with respect to one another.