Abstract: A method of detecting binary information from the pulse-shaped output signal of a CCD uses a varying reference voltage which depends on the amplitude of the last pulse detected, in order to render the detection system immune to pulse distortion as a result of transfer losses in the CCD.

Abstract: A series-parallel-series memory or other parallel-to-series CCD has charge-signals interlaced in alternate parallel channels 1a and 1b, and de-interlacing electrodes (19, 20, 21, 22) at the parallel-to-series transition. In order to avoid delay effects as a result of comb-shaped electrode configurations of the de-interlacing electrodes, and associated complex clock control, a narrow extra electrode (41) is provided between the de-interlacing electrodes and the series-output register (B). This electrode (41) may serve as a buffer electrode for each half row of information (from 1a or 1b) while the preceding half row (from 1b or 1a) is transported through the series output register.

Abstract: The invention relates to an integrated MOS circuit comprising a MOS transistor which is connected as a resistor and which, when conducting current, generates a voltage which is supplied to the source/gate of a second field effect device. In order to obtain a suitable current adjustment, the two channel widths are chosen so that due to narrow channel effects, a difference (though small) in threshold voltage is obtained. The invention is of particular interest for CCD input circuits for generating a small offset voltage required for supplying FAT-zero.

Abstract: In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided, to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information, which is provided by means of pulse duration variation, for adapting the time delay of the memory circuit (FIG. 1).

Abstract: A series/parallel/series shift register memory comprises a substrate on which there are provided storage positions for multivalent data elements. There is provided a redundancy generator for generating one or more redundant code elements on the basis of a group of data elements, said redundant code elements being applied to the series input of the shift register memory later than the associated data elements. The code elements are conducted through parallel-connected storage registers which are shorter than those used for the associated data elements, so that a redundancy reducer receives the redundant code elements from a series output before the associated data elements appear on this series output. The reduction of the storage registers, expressed in periods of the shift drive, can be performed in different ways from a technological point of view.

Abstract: The invention relates to a charge-coupled SPS memory comprising a series input register, a parallel section and a series output register. In order to increase the retention time leakage current drain regions are provided beside the memory. Since the charge collected as a result of leakage current is largest during the transport through the outermost registers of the parallel section, only the sides of the parallel section are screened by the said draining regions which preferably consist of dummy registers. FIG. 1.