Abstract: The present disclosure relates to a ring-oscillator with glitch-free frequency-tuning. The disclosed ring-oscillator at least includes multiple delay stages coupled in series within a ring loop and having a first delay stage, a capacitor bank coupled between an output of the first delay stage and ground, and a timing block configured to receive an output signal of the first delay stage and at least one controlling signal. The at least one controlling signal determines at least one capacitor in the capacitor bank connecting or disconnecting to the ring loop. The timing block is configured to pass or not pass the at least one controlling signal to the capacitor bank based on whether the output signal of the first delay stage meets a certain condition. Therefore, the connection or disconnection of the at least one capacitor does not cause a significant voltage change at the output of the first delay stage.

Abstract: A low leakage level shifter circuit converts a lower voltage signal to a higher voltage signal. The level shifter includes a half-latch with an output node that is toggled between the higher voltage and a reference voltage based on an input signal toggled between the lower voltage and the reference voltage. Crosscoupled transistors keep one of the output node and a complement node charged to the higher voltage by a charge transistor while the other node is discharged by a discharge transistor. To discharge the charged node, current through the discharge transistor needs to be higher than current through the charge transistor, but the discharge transistor is only partially turned on by the lower voltage input signal. First and second resistors coupled between the charge transistors and a voltage source reduce current through the charge transistors, allowing the discharge transistors to be smaller to avoid a high leakage current.

Abstract: The present disclosure relates to a ring-oscillator with glitch-free frequency-tuning. The disclosed ring-oscillator at least includes multiple delay stages coupled in series within a ring loop and having a first delay stage, a capacitor bank coupled between an output of the first delay stage and ground, and a timing block configured to receive an output signal of the first delay stage and at least one controlling signal. The at least one controlling signal determines at least one capacitor in the capacitor bank connecting or disconnecting to the ring loop. The timing block is configured to pass or not pass the at least one controlling signal to the capacitor bank based on whether the output signal of the first delay stage meets a certain condition. Therefore, the connection or disconnection of the at least one capacitor does not cause a significant voltage change at the output of the first delay stage.

Abstract: A transceiver device comprising transceiver circuitry (5) coupled to one or more antenna ports (2; 2?) by a balun arrangement (Lb, Lu; Lu?). For each of the antenna ports (2; 2?) an antenna switch (Ta; Ta?) is present having an antenna enabling input (4; 4?) and being arranged to connect an unbalanced coil (Lu; Lu?) from the balun arrangement (Lb, Lu; Lu?) to the antenna port (2; 2?) and a ground port (3). Also an electro-static discharge (ESD) protection circuit is provided with an ESD switch (Te; Te?) arranged to connect the antenna port (2; 2?) to the antenna enabling input (4; 4?) of the antenna switch (Ta; Ta?). The ESD switch (Te; Te?) has an ESD switch control input (A) connected to an ESD trigger arrangement (Rtrigger).

Abstract: Balun circuitry with a transceiver loop, a first antenna loop, and a second antenna loop is disclosed. The first antenna loop, the second antenna loop, and the transceiver loop are coaxially positioned such that the first antenna loop and the second antenna loop are coupled in opposite phase to the transceiver loop. In at least one exemplary embodiment, a semiconductor substrate has a layer that includes the first antenna loop, the second antenna loop, and the transceiver loop.

Abstract: Frequency synthesizer circuitry includes multi-phase clock generator circuitry, frequency divider circuitry, signal retiming circuitry, and signal combining circuitry. The multi-phase clock generator circuitry receives an input clock signal and generates a number of multi-phase clock signals. The frequency divider circuitry also receives the input clock signal and performs frequency division thereon to generate a reference signal. The signal retiming circuitry receives the reference signal and the multi-phase clock signals and generates a number of retiming signals. The signal combining circuitry combines two of the retiming signals to provide an output clock signal that has the same frequency as the reference signal but a different duty cycle.

Abstract: Balun circuitry with a transceiver loop, a first antenna loop, and a second antenna loop is disclosed. The first antenna loop, the second antenna loop, and the transceiver loop are coaxially positioned such that the first antenna loop and the second antenna loop are coupled in opposite phase to the transceiver loop. In at least one exemplary embodiment, a semiconductor substrate has a layer that includes the first antenna loop, the second antenna loop, and the transceiver loop.

Abstract: A transceiver device comprising transceiver circuitry (5) coupled to one or more antenna ports (2; 2?) by a balun arrangement (Lb, Lu; Lu?). For each of the antenna ports (2; 2?) an antenna switch (Ta; Ta?) is present having an antenna enabling input (4; 4?) and being arranged to connect an unbalanced coil (Lu; Lu?) from the balun arrangement (Lb, Lu; Lu?) to the antenna port (2; 2?) and a ground port (3). Also an electro-static discharge (ESD) protection circuit is provided with an ESD switch (Te; Te?) arranged to connect the antenna port (2; 2?) to the antenna enabling input (4; 4?) of the antenna switch (Ta; Ta?). The ESD switch (Te; Te?) has an ESD switch control input (A) connected to an ESD trigger arrangement (Rtrigger).

Abstract: Balun circuit which is configured in an on-chip design, and multi-port antenna switch circuit comprising such a balun circuit. The balun circuit has a transceiver loop (3), as well as a first antenna loop (1) and at least one further antenna loop (2). The first antenna loop (1), the at least one further antenna loop (2), and the transceiver loop (3) are coaxially positioned in one layer of the on-chip design. The multi-port antenna switch circuit further has a first switch (T1) connected between a ground terminal (A1GND) of the first antenna loop (1) and a first antenna external connection pad (Pg1), and a second switch (T2) connected between a ground terminal (A2GND) of the at least one further antenna loop (2) and at least one further antenna external connection pad (Pg2).

Abstract: Frequency synthesizer circuitry includes multi-phase clock generator circuitry, frequency divider circuitry, signal retiming circuitry, and signal combining circuitry. The multi-phase clock generator circuitry receives an input clock signal and generates a number of multi-phase clock signals. The frequency divider circuitry also receives the input clock signal and performs frequency division thereon to generate a reference signal. The signal retiming circuitry receives the reference signal and the multi-phase clock signals and generates a number of retiming signals. The signal combining circuitry combines two of the retiming signals to provide an output clock signal that has the same frequency as the reference signal but a different duty cycle.

Abstract: Balun circuit which is configured in an on-chip design, and multi-port antenna switch circuit comprising such a balun circuit. The balun circuit has a transceiver loop (3), as well as a first antenna loop (1) and at least one further antenna loop (2). The first antenna loop (1), the at least one further antenna loop (2), and the transceiver loop (3) are coaxially positioned in one layer of the on-chip design. The multi-port antenna switch circuit further has a first switch (T1) connected between a ground terminal (A1GND) of the first antenna loop (1) and a first antenna external connection pad (Pg1), and a second switch (T2) connected between a ground terminal (A2GND) of the at least one further antenna loop (2) and at least one further antenna external connection pad (Pg2).

Abstract: Each coil of a transformer is partitioned into two or more parallel segments. The multiple segments of each coil are interleaved with each other to form a coplanar interleaved transformer that has a greater coupling efficiency than a non-segmented coplanar interleaved transformer. In a preferred embodiment, the multiple segments are of reduced width, so that the interleaved coils consume substantially the same area as the non-segmented coplanar interleaved transformer, thereby maintaining the same inductance as the non-segmented transformer. To provide for maximum efficiency, each segment of each coil is embodied so as to have substantially equal length as each other segment of the coil.

Abstract: An amplifier for use in a mobile phone for supplying a signal (Io) to a load (ZL) comprises a first transistor (T1) having a first main terminal coupled to a reference terminal (GND), a control terminal, and a second main terminal for supplying the signal (Io) to the load (ZL), and sensing means for determining the value of the signal (I0). The sensing means comprises a second transistor (T2) having a first main terminal coupled to the first main terminal of the first transistor (T1), a control terminal coupled to the control terminal of the first transistor (T1), and a second main terminal for supplying a further signal (IF) which is a representation of the signal (Io). The amplifier comprises detection means (DMNS) for supplying a DC-component (IDC2) of the further signal (IF).

Abstract: Each coil of a transformer is partitioned into two or more parallel segments. The multiple segments of each coil are interleaved with each other to form a coplanar interleaved transformer that has a greater coupling efficiency than a non-segmented coplanar interleaved transformer. In a preferred embodiment, the multiple segments are of reduced width, so that the interleaved coils consume substantially the same area as the non-segmented coplanar interleaved transformer, thereby maintaining the same inductance as the non-segmented transformer. To provide for maximum efficiency, each segment of each coil is embodied so as to have substantially equal length as each other segment of the coil.

Abstract: A transceiver for radio frequency signals has a transmit branch and a receive branch that are coupled to an antenna feed point The receive branch has a network with an input node and an output node. The input node is coupled to the antenna feed point and the output node is coupled to a low noise amplifier in the receive branch. The network is configured such that in a transmit node of the transceiver, the input node is switched as an open circuit caused by switching the output node as a short circuit.

Abstract: The invention relates to a semiconductor device comprising a semiconductor body (10) including, for example, a p-type substrate (11) and a PNP bipolar transistor having a collector (1), a base (2) and an emitter (3), which are each provided with a connection conductor (7, 8, 9). One or more of the connection conductors (7, 8, 9) extend over a part of an insulating layer (20) which covers the body (10) which contains, below said insulating layer (20), a further semiconductor region (4) of a conductivity type opposite to that of the substrate (11). A disadvantage of the known device is that it is less suitable for certain applications, such as power amplification. In a device according to the invention, a sub-region (4b) of the further semiconductor region which borders on the substrate (11) is provided with a higher doping concentration than the remainder (4a) of the further semiconductor region (4).