Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n?1], Vsw2[n?1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n?1], Vsw2[n?1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Abstract: A cascode transistor circuit comprising a depletion-mode switch in series with a normally-off switch between a drain output terminal and a source output terminal. The circuit also includes a controller comprising a controller output terminal configured to provide a normally-on control signal for a normally-on control terminal of the depletion-mode switch, wherein the normally-on control signal is independent of the normally-off control signal; a negative voltage source configured to provide a negative voltage to the normally-on control terminal of the depletion-mode switch; and a feedback capacitance between the drain output terminal and a control node in a circuit path between the controller output terminal and the normally-on control terminal of the depletion-mode switch.

Abstract: A cascode transistor circuit comprising a depletion-mode switch in series with a normally-off switch between a drain output terminal and a source output terminal. The circuit also includes a controller comprising a controller output terminal configured to provide a normally-on control signal for a normally-on control terminal of the depletion-mode switch, wherein the normally-on control signal is independent of the normally-off control signal; a negative voltage source configured to provide a negative voltage to the normally-on control terminal of the depletion-mode switch; and a feedback capacitance between the drain output terminal and a control node in a circuit path between the controller output terminal and the normally-on control terminal of the depletion-mode switch.

Abstract: In a method of the invention for providing clock signals to a mixed signal telecommunication chip having a communication signal in a communication signal band, said clock signals comprise a central clock frequency signal and sub-frequency signals which are multiples or divisions of said central clock frequency signal. The central clock frequency signal is selected such that the central clock frequency signal and the sub-frequency signals are located outside the telecommunication signal band. The a mixed signal telecommunication chip of the invention takes advantage of the above clock planning.