Abstract: Our invention concerns with ready-to-use non dairy creams with good storage stability, containing egg yolk and eggwhite. In fact, the composition of our creams is:0.05-0.5 wt % emulsifier0.5-8.0 wt % egg yolk0.01-1.0 wt % caseinate0.5-4.0 wt % egg white0-1.0 wt % thickener1-10 wt % carbohydrate25-45 wt % fatbalance: waterThe creams are sterile and display a water activity of 0.95-1.0.Also a process for the preparation of such non dairy creams is part of the invention.

Abstract: A coupling network for a data processor is described, including, one or more cross bar switches having inputs and outputs and one or more arrays of silos. A series connection is formed in which these components are alternately arranged in a succession having at least three elements. A retrocoupling network is used for coupling outputs of a data processor to its inputs, and it also provides external communication. The configuration offers ample freedom of mapping, notably in cyclostatic processors.

Abstract: A data processing system buffers sequential data for the duration of cyclically recurrent delay times. Memory location allocation is performed in such a way, that the memory is used efficiently without data-shifting after a read-out, and that the address generator is fairly simple.

Abstract: The invention describes a processor system suitable for processing video signal samples on a real-time basis. Signals are derived from the samples for driving an imaging unit. For this purpose, one or more processor modules are provided with processor elements, operating in parallel in time, which are connected to a crossbar switch. A module contains at least one arithmetic/logic processor element and at least one memory processor element. Moreover, there is a clock device, the frequency of which bears a fixed relationship to the frequency with which the video signal samples are obtained.

Abstract: A data processor system having at least one arithmetic/logic processor element and at least one memory processor element which can be coupled in circuit using a crossbar switch. The arithmetic/logic processor element is provided with an ALU and a program memory. The ALU has an input for instructions. The instructions can be made up of data from the program memory and data from the crossbar switch via a channel specifically present for the purpose.

Abstract: A processor system having one or more stations (22, 24, 26) which are interconnected by a general communication network (20). Each station has one or more processors (34, 36). Superprocesses (74, 76, 78) which have one or more processes (80-90) can be executed in the stations. Each superprocess is provided with mail-box space (50, 52, 54) for communication with the environment, in which mail-box space the relevant superprocess and other superprocesses can write but in which only the relevant superprocess itself can read. Processes within the same superprocess have variable data in common, but their register stacks are private. Each mail-box is provided with a filling indicator. In the case of a read operation in an empty mail-box space, a wait signal is issued for the initiating process; write operations in a full mail-box space produce an error signal. There is also provided a job control system for allocating jobs among the stations by way of an application load file.

Abstract: Fibers containing casein and at least one heat-settable protein are prepared by dry-spinning an aqueous protein mixture containing calcium- and phosphate ions at a temperature below the gelling point of the protein mixture and drying the fibers obtained. The fibers are hydrated, and incorporated into a meat analogue mixture as texture-imparting materials.

Abstract: Fibres containing casein and at least one heat-settable protein are prepared by dry-spinning an aqueous protein mixture containing calcium- and phosphate ions at a temperature below the gelling point of the protein mixture and drying the fibres obtained.