Patents by Inventor Hendrik F.W. Dekkers
Hendrik F.W. Dekkers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230382756Abstract: A mixed metal oxide and methods for making the mixed metal oxide are disclosed. The mixed metal oxide includes metal and metalloid elements including 0.40 to 0.70 parts by mole Mg, 0.30 to 0.60 parts by mole Zn, and 0.00 to 0.30 parts by mole of other elements selected from metals and metalloids, wherein less than 0.01 parts by mole of the other elements is Al, and wherein less than 0.04 parts by mole of the other elements is Ga. The sum of all parts by mole of Mg, Zn, and the other elements may amount to about 1.00. The mixed metal oxide additionally includes) oxygen and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.Type: ApplicationFiled: May 26, 2023Publication date: November 30, 2023Inventors: Michiel Jan Van Setten, Geoffrey Pourtois, Hendrik F.W. Dekkers, Gouri Sankar Kar
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Publication number: 20230382758Abstract: Mixed metal oxides and methods for making the mixed metal oxides are disclosed. A mixed metal oxide includes metal or metalloid elements including 0.50 to 0.90 parts by mole Mg, 0.05 to 0.30 parts by mole Al, 0.01 to 0.20 parts by mole Sb, and 0.00 to 0.31 parts by mole of other elements selected from metals and metalloids. The sum of all parts by mole of Mg, Al, Sb, and the other elements selected from metals and metalloids may amount to about 1.00. The mixed metal oxide additionally includes oxygen, and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.Type: ApplicationFiled: May 30, 2023Publication date: November 30, 2023Inventors: Michiel Jan van Setten, Geoffrey Pourtois, Hendrik F.W. Dekkers, Gouri Sankar Kar
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Patent number: 11702731Abstract: A method for forming a film of an oxide of In, Ga, and Zn, having a spinel crystalline phase comprises providing a substrate in a chamber; providing a sputtering target in said chamber, the target comprising an oxide of In, Ga, and Zn, wherein: In, Ga, and Zn represent together at least 95 at % of the elements other than oxygen, In represents from 0.6 to 44 at % of In, Ga, and Zn, Ga represents from 22 to 66 at % of In, Ga, and Zn, and Zn represents from 20 to 46 at % of In, Ga, and Zn; and forming a film on the substrate, the substrate being at a temperature of from 125° C. to 250° C., by sputtering the target with a sputtering gas comprising O2, the sputtering being performed at a sputtering power of at least 200 W.Type: GrantFiled: November 25, 2020Date of Patent: July 18, 2023Assignees: IMEC vzw, Applied Materials Inc.Inventors: Hendrik F. W. Dekkers, Jose Ignacio del Agua Borniquel
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Publication number: 20230010899Abstract: In an aspect, a mixed metal oxide comprises or consists essentially of: a mixture comprises or consisting essentially of 0.30 to 0.69 parts by mole Mg, 0.20 to 0.69 parts by mole Zn, 0.01 to 0.30 parts by mole of a third element selected from Al and Ga, and, either, when the third element is Al, 0.00 to 0.31 parts by mole of other elements selected from metals and metalloids, or, when the third element is Ga, 0.00 to 0.15 parts by mole of other elements selected from metals and metalloids, wherein the sum of all parts by mole of Mg, Zn, the third element, and the other elements amounts to 1.00, wherein the amount in parts by mole of the other elements is lower than the amount in parts by mole of Mg and is lower than the amount in parts by mole of Zn; oxygen; and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.Type: ApplicationFiled: July 1, 2022Publication date: January 12, 2023Inventors: Michiel Jan van Setten, Hendrik F.W Dekkers, Karl Opsomer, Geoffrey Pourtois, Gouri Sankar Kar
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Patent number: 11430898Abstract: Methods and apparatus for forming a thin film transistor (TFT) having a metal oxide layer. The method may include forming an amorphous metal oxide layer and treating the metal oxide layer with a silicon containing gas or plasma including Si4+ ions. The silicon treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.Type: GrantFiled: March 13, 2020Date of Patent: August 30, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Jose-Ignacio Del-Agua-Borniquel, Hendrik F. W. Dekkers, Hans Van Meer, Jae Young Lee
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Publication number: 20210288186Abstract: Methods and apparatus for forming a thin film transistor (TFT) having a metal oxide layer. The method may include forming an amorphous metal oxide layer and treating the metal oxide layer with a silicon containing gas or plasma including Si4+ ions. The silicon treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.Type: ApplicationFiled: March 13, 2020Publication date: September 16, 2021Inventors: Jose-Ignacio Del-Agua-Borniquel, Hendrik F.W. Dekkers, Hans Van Meer, Jae Young Lee
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Patent number: 11075083Abstract: A method for forming a gate stack of a field-effect transistor includes depositing a Si capping layer on a Ge channel material (100). The method further includes depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature less than or equal to 200° C., and a plasma power less than or equal to 100 W.Type: GrantFiled: November 22, 2019Date of Patent: July 27, 2021Assignee: IMEC vzwInventors: Hiroaki Arimura, Antony Premkumar Peter, Hendrik F. W. Dekkers
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Publication number: 20210164091Abstract: A method for forming a film of an oxide of In, Ga, and Zn, having a spinel crystalline phase comprises providing a substrate in a chamber; providing a sputtering target in said chamber, the target comprising an oxide of In, Ga, and Zn, wherein: In, Ga, and Zn represent together at least 95 at % of the elements other than oxygen, In represents from 0.6 to 44 at % of In, Ga, and Zn, Ga represents from 22 to 66 at % of In, Ga, and Zn, and Zn represents from 20 to 46 at % of In, Ga, and Zn; and forming a film on the substrate, the substrate being at a temperature of from 125° C. to 250° C., by sputtering the target with a sputtering gas comprising O2, the sputtering being performed at a sputtering power of at least 200 W.Type: ApplicationFiled: November 25, 2020Publication date: June 3, 2021Applicants: IMEC VZW, Applied Materials Inc.Inventors: Hendrik F.W. Dekkers, Jose Ignacio del Agua Borniquel
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Publication number: 20200203168Abstract: A method for forming a gate stack of a field-effect transistor includes depositing a Si capping layer on a Ge channel material (100). The method further includes depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature less than or equal to 200° C., and a plasma power less than or equal to 100 W.Type: ApplicationFiled: November 22, 2019Publication date: June 25, 2020Inventors: Hiroaki Arimura, Antony Premkumar Peter, Hendrik F.W. Dekkers
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Patent number: 10607896Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set.Type: GrantFiled: May 10, 2017Date of Patent: March 31, 2020Assignee: IMEC vzwInventors: Lars-Ake Ragnarsson, Hendrik F.W. Dekkers, Tom Schram, Julien Ryckaert, Naoto Horiguchi, Mustafa Badaroglu
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Patent number: 9892923Abstract: The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose effective work function can be tuned. In one aspect, a method of forming a metal electrode of a semiconductor structure includes providing a semiconductor substrate having at least a region covered with a dielectric. The semiconductor substrate is introduced into a chamber configured for atomic layer deposition (ALD). A metal for the metal electrode is deposited at least on the dielectric by performing an ALD cycle. Performing the ALD cycle includes pulsing a Ti-containing precursor gas followed by pulsing a Ta-containing precursor gas, and further includes pulsing NH3 gas.Type: GrantFiled: December 22, 2015Date of Patent: February 13, 2018Assignee: IMEC vzwInventors: Hendrik F. W. Dekkers, Lars-Ake Ragnarsson, Tom Schram
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Publication number: 20170330801Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set.Type: ApplicationFiled: May 10, 2017Publication date: November 16, 2017Inventors: Lars-Ake Ragnarsson, Hendrik F.W. Dekkers, Tom Schram, Julien Ryckaert, Naoto Horiguchi, Mustafa Badaroglu
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Publication number: 20160196976Abstract: The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose effective work function can be tuned. In one aspect, a method of forming a metal electrode of a semiconductor structure includes providing a semiconductor substrate having at least a region covered with a dielectric. The semiconductor substrate is introduced into a chamber configured for atomic layer deposition (ALD). A metal for the metal electrode is deposited at least on the dielectric by performing an ALD cycle. Performing the ALD cycle includes pulsing a Ti-containing precursor gas followed by pulsing a Ta-containing precursor gas, and further includes pulsing NH3 gas.Type: ApplicationFiled: December 22, 2015Publication date: July 7, 2016Inventors: Hendrik F.W. DEKKERS, Lars-Ake RAGNARSSON, Tom SCHRAM
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Patent number: 9287273Abstract: The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.Type: GrantFiled: June 8, 2015Date of Patent: March 15, 2016Assignee: IMEC VZWInventors: Lars-Ake Ragnarsson, Tom Schram, Hendrik F. W. Dekkers, Soon Aik Chew
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Publication number: 20150357244Abstract: The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.Type: ApplicationFiled: June 8, 2015Publication date: December 10, 2015Inventors: Lars-Ake Ragnarsson, Tom Schram, Hendrik F.W. Dekkers, Soon Aik Chew