Patents by Inventor Hendrik Pieter Hochstenbach

Hendrik Pieter Hochstenbach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9466579
    Abstract: The present application relates to a reinforcing structure for reinforcing a stack of layers in a semiconductor component, wherein at least one reinforcing element having at least one integrated anchor-like part, is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 11, 2016
    Assignee: NXP B.V.
    Inventors: Hendrik Pieter Hochstenbach, Willem Dirk Van Driel
  • Patent number: 8268672
    Abstract: An assembly (100) is provided comprising a first chip (20) and a second chip (30) which are interconnected through solder connections. These comprise, at the first chip, an underbump metallization and a solder bump, and, at the second chip, a metallization. In this case the solder bump is provided as a fluid layer with a contact angle of less than 90° C., and an intermetallic compound is formed on the basis of the metallization at the second chip, and at least one element of the composition is applied as the solder bump.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: September 18, 2012
    Assignee: NXP B.V.
    Inventors: Nicolaas Johannes Anthonius Van Veen, Hendrik Pieter Hochstenbach
  • Publication number: 20110275176
    Abstract: An assembly (100) is provided comprising a first chip (20) and a second chip (30) which are interconnected through solder connections. These comprise, at the first chip, an underbump metallisation and a solder bump, and, at the second chip, a metallisation. In this case the solder bump is provided as a fluid layer with a contact angle of less than 90° C., and an intermetallic compound is formed on the basis of the metallisation at the second chip, and at least one element of the composition is applied as the solder bump.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 10, 2011
    Inventors: Nicolaas Johannes Anthonius Van Veen, Hendrik Pieter Hochstenbach
  • Publication number: 20110192885
    Abstract: Consistent with an example embodiment, a wirebonding process comprises forming a bond pad with a roughened upper surface, lowering a copper wirebond ball onto the roughened bond bad, and applying a force to the wirebond ball against the roughened surface, A heat treatment is applied to form the bond between the wirebond ball and the roughened surface, wherein the bond is formed without use of ultrasonic energy. This process avoids the use of ultrasonic welding and thereby reduces the occurrence of microcracks and resulting Chip Out of the Bond (COUB) and Metal Peel Off (MPO) failures. The roughened surface of the bond pad improves the reliability of the connection.
    Type: Application
    Filed: December 23, 2010
    Publication date: August 11, 2011
    Applicant: NXP B.V.
    Inventors: Hendrik Pieter HOCHSTENBACH, Willem Dirk van DRIEL, Eric OOMS
  • Publication number: 20100193945
    Abstract: The present application relates to a reinforcing structure (1, 2) for reinforcing a stack of layers (100) in a semiconductor component, wherein at least one reinforcing element (110, 118) having at least one integrated anchor-like part (110a, 110b), is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.
    Type: Application
    Filed: July 17, 2008
    Publication date: August 5, 2010
    Applicant: NXP B.V.
    Inventors: Hendrik Pieter Hochstenbach, Willem Dirk Van Driel
  • Patent number: 7196416
    Abstract: The electronic device (100) is a chip-on-chip construction on a lead frame (10) comprising a heat sink (13) in an encapsulation (80). The first chip (20) and the second chip (30) are mutually connected by first conductive interconnections (24) and the first chip (20) is connected to the lead frame (10) by second conductive interconnections (27) which preferably have a lower reflow temperature than the first conductive interconnections (24). By heating the device (100) the adhesive layer (25) will first shrink, causing a stress, which will be relaxated by reflowing the second conductive interconnections (27).
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: March 27, 2007
    Assignee: NXP B.V.
    Inventors: Hendrik Pieter Hochstenbach, Andrea Henricus Maria Van Eck, Rintje Van Der Meulen