Abstract: Methods of and apparatuses for performing electromigration risk analyses of power interconnect systems in integrated circuits employ a pseudo dynamic simulation model, whereby all transistor gates of a transistor network coupled to the power interconnect system are switched at the same time. To accomplish simultaneity in switching, a netlist characterizing the transistor network is altered in a manner that all gates are connected to a common input signal node. Time dependent currents drawn by transistors of the transistor network connected to the power interconnect system are determined. The time dependent currents and dimensional characteristics gleaned from the layout of the integrated circuit are used to calculate peak, average, or RMS current densities. The current densities are compared to electromigration rules to determine what areas of the power interconnect system may be in violation of the electromigration rules.

Abstract: Methods of and apparatuses for performing electromigration risk analyses of power interconnect systems in integrated circuits employ a pseudo dynamic simulation model, whereby all transistor gates of a transistor network coupled to the power interconnect system are switched at the same time. To accomplish simultaneity in switching, a netlist characterizing the transistor network is altered in a manner that all gates are connected to a common input signal node. Time dependent currents drawn by transistors of the transistor network connected to the power interconnect system are determined. The time dependent currents and dimensional characteristics gleaned from the layout of the integrated circuit are used to calculate peak, average, or RMS current densities. The current densities are compared to electromigration rules to determine what areas of the power interconnect system may be in violation of the electromigration rules.

Abstract: The present disclosure relates to a method for estimating input voltages to transistors in a transistor network. The method includes identifying an input signal, to transforming a netlist, identifying input parameters and simulating a plurality of interconnected transistors. The method also can include determining if a signal is internal to a signal net, disconnecting the driver of the signal net and estimate the load based on the load of the signal net. The method also relates to circuits, specifically integrated circuits, produced by the method taught. The method is particularly applicable to the design of circuits such as VLSI integrated circuits. The disclosure also relates to electrical products such as computer systems or integrated circuit boards including a circuit designed by the method taught.

Abstract: A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.

Abstract: A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.

Abstract: A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. Calculation of the mean time to failure can include the current density and the temperature. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit based on temperature effects. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.