Abstract: The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by prolonging the transfer time for data from the master to the salve section of the flip-flop circuit.

Abstract: A gate array circuit includes a row of consecutively arranged n-channel transistors and an adjacent row of p-channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at least three times the width of the narrow transistors. The gate electrodes are common to the three subrows. Preferably, the wide subrow is arranged centrally between the narrow subrows. This construction affords the advantage of a very high density and a very high flexibility in designing the functions to be realized.

Abstract: A master slice semiconductor integrated circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same row are controlled via one and the same word line. The circuit includes row selection means, for example, an exclusive-OR circuit for each row, for selecting either a single row of NMOS cells or a single row of PMOS cells.

Abstract: The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2.times.2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.

Abstract: In relatively large systems of (integrated) circuits, data signals can experience a delay which is in the order of magnitude of a clock-pulse period. The receiving circuit (i.e. receiving the data signal) then receives the data signal too late (the clock pulse has ceased) and can at that moment no longer take over the data signal for further processing or transport. In the system according to the invention the clock pulses are led via a delaying element (for example, the inverting circuits in series) to the receiving circuit (slave of the master/slave flip-flop). The data output of the receiving circuit is connected to a data input of another circuit (master of another master/slave flip-flop), which receives the undelayed clock pulses, the data delay between the receiving circuit and the other circuit being negligible. The data delay is thus distributed over two clock pulses.

Abstract: In CMOS integrated circuits, "latch-up" problems may arise if no special steps are taken. One way to counteract a "latch-up" state is to apply a substrate bias voltage. In an integrated circuit, an externally-clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2V. As a result, the integrated circuit becomes less sensitive to "latch-up", especially during measuring and testing procedures, in which no external clock signal is supplied.

Abstract: In integrated circuits the delay of the signal transitions has to lie within specified limits. This delay is partly determined by variations in the manufacturing process (process scatter). To compensate for the effect of this scatter a load capacitance is connected via a switching element to a node which is to be influenced in the integrated circuit. The switching element receives a reference voltage which is dependent on the manufacturing process and is generated by reference source, so that the node capacitance 26 is connected to the node for a longer or shorter time, depending on the process scatter.

Abstract: A logic circuit incorporating carry look-ahead in which efficiency can be achieved regarding the hardware for generating the sum signals and carry signals by a suitable choice of the adder gate, making use of the already present signal a.sub.1 .multidot.b.sub.i which is used for generating the carry look-ahead signal.

Abstract: The invention relates to a CCD input and reference charge generator, in which the occurrence of electron injection into the substrate (due to cross-talk to the substrate) and hence undesired signal distortions is prevented. For this purpose, the generator is provided with a voltage divider (26) which is constituted at least for a part (28) by a resistance element arranged outside the substrate, for example, by a polycrystalline silicon resistor. Thus, it is achieved that input diode zones (11) are no longer connected to the substrate voltage.

Abstract: Charge-coupled devices are very sensitive to clock cross-talk due to the overlap between successive electrodes. The influence of this cross-talk is reduced when the clock lines are periodically connected to ground by a low-ohmic impedance. For this purpose, each clock line is controlled from a buffer, whose output is connected to a clock line. A clamping transistor is connected between the output and ground. When this clamping transistor is controlled by means of the output signal and at the same time by the input signal of the buffer, the output is clamped to ground at the instant at which the cross-talk is expected by means of only a single clamping transistor.

Abstract: An integrated logic circuit includes a push-pull amplifier stage, in which by means of a bootstrap circuit the potential at the gate of the "push" transistor is brought above the supply voltage so that the output voltage of the amplifier lies above the supply voltage minus the threshold voltage of the push transistor. In order to prevent the charge from leaking away after the bootstrap capacitance has been charged via an enhancement transistor, the enhancement transistor is cut off by means of the "low" input signal. A second bootstrap circuit (between the input and the gate of the enhancement transistor) ensures that the first bootstrap capacitance is charged up to the full supply voltage because the latter gate electrode is lifted above the supply voltage by the second bootstrap.

Abstract: A device is described for electronically executing a mathematical operation, being Z=KA+(1-K)B. It is also described how this device or how several of such devices can be used for the design of a number of realizations, such as a recursive filter, a digital mixer etc. The basic idea is the electronic implementation of a mathematical function for binary variables.