Abstract: A probe card device comprises a testing circuit board, at least one probe and an image capture module. The testing circuit board has a first surface and a second surface in opposite. The at least one probe is disposed on the first surface of the testing circuit board and electrically connected to the testing circuit board. The at least one probe has a probe head and the probe head has a first height to the first surface. The image capture module is disposed on the first surface of the testing circuit board, and is located adjacent to the probe. The image capture module has a head portion and the head portion has a second height to the first surface. Wherein, the second height is smaller than the first height, and the image capture module is aligned to the probe head to capture a visible light image from the probe head.

Abstract: The present invention provides a measuring method for prolonging a usage lifetime of a biosensor to measure a physiological signal representative of a physiological parameter associated with an analyte in a biofluid. The biosensor includes two working electrodes at least partially covered by a chemical reagent and two counter electrodes having silver and a silver halide, and each silver halide has an initial amount.

Abstract: Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.

Abstract: The present invention provides a micro biosensor for reducing a measurement interference when measuring a target analyte in the biofluid, including: a substrate; a first working electrode configured on the surface, and including a first sensing section; a second working electrode configured on the surface, and including a second sensing section which is configured adjacent to at least one side of the first sensing section; and a chemical reagent covered on at least a portion of the first sensing section for reacting with the target analyte to produce a resultant. When the first working electrode is driven by a first working voltage, the first sensing section measures a physiological signal with respect to the target analyte. When the second working electrode is driven by a second working voltage, the second conductive material can directly consume the interferant so as to continuously reduce the measurement inference of the physiological signal.

Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.

Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.

Abstract: The present invention provides a micro biosensor for reducing a measurement interference when measuring a target analyte in the biofluid, including: a substrate; a first working electrode configured on the surface, and including a first sensing section; a second working electrode configured on the surface, and including a second sensing section which is configured adjacent to at least one side of the first sensing section; and a chemical reagent covered on at least a portion of the first sensing section for reacting with the target analyte to produce a resultant. When the first working electrode is driven by a first working voltage, the first sensing section measures a physiological signal with respect to the target analyte. When the second working electrode is driven by a second working voltage, the second conductive material can directly consume the interferant so as to continuously reduce the measurement inference of the physiological signal.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: An in-memory computing circuit includes an initial computing circuit and a target computing circuit. Herein, the initial computing circuit is configured to perform first operation processing on first data and second data to output a first operation result, and perform second operation processing on the first data and the second data to output a second operation result. The target computing circuit is configured to perform the first operation processing on the second operation result and the first operation result to output a first target result, and perform the second operation processing on the first data and the second operation result to output a second target result.

Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a fabrication method thereof, and a memory. The semiconductor structure includes: a base substrate including a first side and a second side opposite to each other; a first device layer including a first device, the first device layer being arranged on the first side of the base substrate; and a second device layer including a second device, the second device layer being arranged on the second side of the base substrate. At least part of the first device and at least part of the second device share a first doped region.

Abstract: An in-memory computing method is applied to the in-memory computing circuit. The in-memory computing circuit includes a plurality of first memory cells, a plurality of second memory cells, and a sense amplifier. Level state control is performed on the plurality of first memory cells according to first data to output a first voltage; level state control is performed on the plurality of second memory cells according to second data to output a second voltage; and after receiving a predetermined operation instruction, the sense amplifier receives the first voltage and the second voltage, compares the first voltage with the second voltage, and determines a comparison result of the first data and the second data according to a comparison result of the first voltage and the second voltage.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate; bit lines positioned in the substrate, where each of the bit lines includes a conductive body and a dielectric layer, the conductive body includes a body portion and a plurality of contact portions, the body portion extend along a first direction, the contact portions protrude from a side surface of the body portion facing away from a bottom of the substrate, the contact portions are arranged at intervals along the first direction, and the dielectric layer covers side wall surfaces on left and right sides of the body portion along an extension direction; and transistors positioned on top surfaces of the contact portions facing away from the body portion, and extension directions of channels of the transistors are perpendicular to a plane where the substrate is positioned.

Abstract: A semiconductor structure includes: a substrate; bit lines located in the substrate and including a main body and a plurality of contact portions, the main body extending in a first direction, the contact portions being connected to the main body and extending toward the top surface of the substrate, and the plurality of contact portions being arranged at intervals in the first direction; and transistors located on a top surface of the contact portion, the extension direction of a channel of the transistor being perpendicular to a plane where the substrate is located.

Abstract: The present invention provides a sensing structure of a micro biosensor for performing a measurement of a physiological parameter of a target analyte of a biofluid and reducing an interference of an interferant of the biofluid on the measurement by an electrochemical reaction. The sensing structure includes: a substrate having a surface; a first working electrode configured on the surface, and including an active surface; at least one second working electrode configured on the surface and adjacent to the first working electrode, for consuming the interferant by the electrochemical reaction; and an isolated layer configured with respect to the active surface to program a diffusive distribution of the interferant when the biofluid flows through the second working electrode, wherein at least the interferant of the biofluid passes through the second working electrode over a time period and is consumed by the second working electrode by the electrochemical reaction.

Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.

Abstract: Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.

Abstract: A memory test method and apparatus, an electronic device, and a computer-readable storage medium are provided. The method includes: obtaining a test instruction; generating, in response to the test instruction, a test clock signal, a to-be-tested address and to-be-tested data; determining a to-be-tested memory from memories of a storage device, the storage device including a self-test circuit; writing the to-be-tested data into a storage unit corresponding to the to-be-tested address of the to-be-tested memory; reading output data from the storage unit corresponding to the to-be-tested address of the to-be-tested memory; and comparing the to-be-tested data and the output data to obtain a test result of the to-be-tested memory. The self-test circuit disposed in the storage device is used to implement a memory test process. Thus, the dependency on automatic test equipment is reduced, thereby improving test speed and reducing test cost.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.