Patents by Inventor Heng Hsieh
Heng Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11197794Abstract: The present invention discloses a turning air mattress, a turning air cell, and a control method for a turning air mattress. With structural arrangements of an upper portion and a lower portion of the turning air cell as well as inflation and deflation control, the turning air cell having an upper portion that is wider and a lower portion that is narrower can further assist a patient in body turning, enabling the patient to easily achieve a sufficient body turning angle, further reducing the risk of likeliness to pressure sores caused by the structure of the air mattress pressing against the body of the patient.Type: GrantFiled: August 12, 2019Date of Patent: December 14, 2021Assignee: APEX MEDICAL CORP.Inventors: Ming-Lung Chang, Ming-Heng Hsieh, Wen-Ching Cheng, Pi-Kai Lee, Yu-Chen Liu, Fang-Ju Chou
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Publication number: 20210366895Abstract: Provided is a tap cell including a substrate, a first well, a second well, a first doped region, and the second doped region. The substrate has a first region and a second region. The first well has a first dopant type and includes a first portion disposed in the first region and a second portion extending into the second region. The second well has a second dopant type and includes a third portion disposed in the second region and a fourth portion extending into the first region. The first doped region having the first dopant type is disposed in the second portion of the first well and the third portion of the second well along the second region. The second doped region having the second dopant type is disposed in the first portion of the first well and the fourth portion of the second well along the first region.Type: ApplicationFiled: May 21, 2020Publication date: November 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TAIWANInventors: Yung-Feng Chang, Bao-Ru Young, Tung-Heng Hsieh, Chun-Chia Hsu
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Patent number: 11177382Abstract: A method and structure for mitigating strain loss (e.g., in a FinFET channel) includes providing a semiconductor device having a substrate having a substrate fin portion, an active fin region formed over a first part of the substrate fin portion, a pickup region formed over a second part of the substrate fin portion, and an anchor formed over a third part of the substrate fin portion. In some embodiments, the substrate fin portion includes a first material, and the active fin region includes a second material different than the first material. In various examples, the anchor is disposed between and adjacent to each of the active fin region and the pickup region.Type: GrantFiled: December 24, 2019Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sheng-Hsiung Wang, Yung Feng Chang, Tung-Heng Hsieh
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Publication number: 20210280572Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction and having a first portion and a second portion separated from each other. The integrated circuit further includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit further includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, wherein the first section extends in the second direction. The conductive feature further includes a second section electrically connected to the second gate electrode structure, wherein the second section extends in the second direction. The conductive feature further includes a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.Type: ApplicationFiled: May 11, 2021Publication date: September 9, 2021Inventors: Tung-Heng HSIEH, Ting-Wei CHIANG, Chung-Te LIN, Hui-Zhong ZHUANG, Li-Chun TIEN, Sheng-Hsiung WANG
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Publication number: 20210264090Abstract: In some embodiments, the present disclosure relates to a method that includes removing portions of a substrate to form a continuous fin over the substrate. Further, a doping process is performed to selectively increase a dopant concentration of a first portion of the continuous fin. A first gate electrode is formed over a second portion of the continuous fin, and a second gate electrode is formed over a third portion of the continuous fin. The first portion of the continuous fin is between the second portion and the third portion of the continuous fin. A dummy gate electrode is formed over the first portion of the continuous fin. Upper portions of the continuous fin that are arranged between the first gate electrode, the second gate electrode, and the dummy gate electrode are removed, and source/drain regions are formed between the first, the second, and the dummy gate electrodes.Type: ApplicationFiled: November 25, 2020Publication date: August 26, 2021Inventors: Chun-Yen Lin, Bao-Ru Young, Tung-Heng Hsieh
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Publication number: 20210257351Abstract: An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.Type: ApplicationFiled: June 16, 2020Publication date: August 19, 2021Inventors: Yung Feng Chang, Bao-Ru Young, Yu-Jung Chang, Tzung-Chi Lee, Tung-Heng Hsieh, Chun-Chia Hsu
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Publication number: 20210249409Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.Type: ApplicationFiled: April 26, 2021Publication date: August 12, 2021Inventors: Chia-Sheng Fan, Bao-Ru Young, Tung-Heng Hsieh
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Patent number: 11075164Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.Type: GrantFiled: November 6, 2019Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Sheng-Hsiung Wang
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Publication number: 20210226023Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.Type: ApplicationFiled: April 5, 2021Publication date: July 22, 2021Inventors: Yi-Jyun HUANG, Tung-Heng HSIEH, Bao-Ru YOUNG
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Publication number: 20210192121Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.Type: ApplicationFiled: March 8, 2021Publication date: June 24, 2021Inventors: Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young, Yung Feng Chang
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Patent number: 11043572Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.Type: GrantFiled: January 13, 2020Date of Patent: June 22, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzung-Chi Lee, Tung-Heng Hsieh, Bao-Ru Young, Chia-Sheng Fan
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Patent number: 11031334Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.Type: GrantFiled: September 6, 2019Date of Patent: June 8, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Heng Hsieh, Ting-Wei Chiang, Chung-Te Lin, Hui-Zhong Zhuang, Li-Chun Tien, Sheng-Hsiung Wang
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Publication number: 20210166977Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: ApplicationFiled: February 8, 2021Publication date: June 3, 2021Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young
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Patent number: 11024622Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.Type: GrantFiled: December 20, 2019Date of Patent: June 1, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien
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Patent number: 11004842Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.Type: GrantFiled: October 21, 2019Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzung-Chi Lee, Tung-Heng Hsieh, Bao-Ru Young, Yung Feng Chang
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Patent number: 10998304Abstract: A conductive line structure includes two conductive lines in a layout. The two cut lines are over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive.Type: GrantFiled: April 22, 2019Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
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Patent number: 10991691Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.Type: GrantFiled: December 20, 2019Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Sheng Fan, Bao-Ru Young, Tung-Heng Hsieh
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Patent number: 10971588Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact layer and a separation layer. The fin structure protrudes from an isolation insulating layer disposed over a substrate and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact layer is disposed on the first source/drain region. The separation layer is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact layer are in contact with a same face of the separation layer.Type: GrantFiled: October 11, 2019Date of Patent: April 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
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Publication number: 20210098369Abstract: The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction. The method further includes identifying the via rail, the source contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout. The method further includes determining a position, length, and width of a jog via to be added to the IC design layout. The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout and generating a tape-out for fabricating a modified mask.Type: ApplicationFiled: July 30, 2020Publication date: April 1, 2021Inventors: Hao Kuang, Tung-Heng Hsieh, Sheng-Hsiung Wang, Bao-Ru Young, Wang-Jung Hsueh, Pang-Chi Wu
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Patent number: 10957604Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.Type: GrantFiled: September 11, 2019Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chieh Wu, Pang-Chi Wu, Kuo-Yi Chao, Mei-Yun Wang, Hsien-Huang Liao, Tung-Heng Hsieh, Bao-Ru Young