Patents by Inventor Heng-Jen Lee
Heng-Jen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120180823Abstract: An apparatus includes a wafer stage configured to secure a wafer; and a cleaning module including a tank adjacent to the wafer stage, and is positioned outside the region occupied by the wafer. The cleaning module is configured to receive de-ionized (DI) water into the tank and extract the DI water out of the tank. The tank is configured to hold DI water with a top surface of the DI water substantially level with a top surface of the wafer.Type: ApplicationFiled: January 18, 2011Publication date: July 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Chun Peng, Heng-Jen Lee
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Publication number: 20120180813Abstract: A wafer chuck is cleaned using a cleaning cap to remove processing residue and particulate matter. The cleaning cap is configured to overlie and align with the wafer chuck and includes a base and a first roller connected to the base and having wound therearound a cleaning cloth. The cleaning cap further includes a second roller connected to the base and having attached thereto a free end of the cleaning cloth. During use, the cleaning cloth winds upon the second roller from the first roller when the second roller rotates about its axis. The cleaning cap can be positioned relative the wafer chuck by way of a manipulator to ensure the cleaning cloth contacts the wafer chuck with sufficient force. The cleaning cloth rubs the wafer chuck with both translational motion and rotational motion.Type: ApplicationFiled: January 18, 2011Publication date: July 19, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Chun Peng, Heng-Jen Lee
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Patent number: 8183701Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.Type: GrantFiled: July 29, 2009Date of Patent: May 22, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yuan Shih, Sophia Wang, Heng-Hsin Liu, Heng-Jen Lee
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Patent number: 8101340Abstract: A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.Type: GrantFiled: May 9, 2007Date of Patent: January 24, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Yu Chang, Heng-Jen Lee, Chin-Hsiang Lin, Hua-Tai Lin, Kuei Shun Chen, Bang-Chein Ho, Li-Kong Turn, Hung-Jui Kuo, Ko-Bin Kao, Tsung-Chih Chien
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Patent number: 8101530Abstract: A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.Type: GrantFiled: September 25, 2009Date of Patent: January 24, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Hsiung Huang, Chin-Hsiang Lin, Heng-Jen Lee, Heng-Hsin Liu
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Publication number: 20110194086Abstract: A wafer edge exposure module connected to a semiconductor wafer track system. The wafer edge exposure module includes a wafer spin device, an optical system, a scanner interface module, and a controller. The wafer spin device supports a wafer for processing. The optical system directs exposure light on a respective edge portion of the wafer simultaneously to create a dummy track on the edge of the wafer. The scanner interface module sends and/or receives dummy edge exposure information from a scanner via a computer network. The controller receives the dummy edge exposure information from the scanner interface module and uses the exposure information to control the optical system.Type: ApplicationFiled: February 9, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Chih CHIEN, Yung-Cheng CHEN, Heng-Jen LEE
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Publication number: 20110161893Abstract: The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired.Type: ApplicationFiled: December 22, 2010Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: CHIN-HSIANG LIN, Heng-Jen Lee, I-Hsiung Huang, Chih-Chiang Tu, Chun-Jen Chen, Rick Lai
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Publication number: 20110159410Abstract: The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Hsiang Lin, Heng-Jen Lee, I-Hsiung Huang, Chih-Chiang Tu, Chun-Jen Chen, Rick Lai
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Publication number: 20110083496Abstract: A method and apparatus provide for simultaneously moving multiple semiconductor wafers in opposite directions while simultaneously performing processing operations on each of the wafers. The semiconductor wafers are orientated in coplanar fashion and are disposed on stages that simultaneously translate in opposite directions to produce a net system momentum of zero. The die of the respective semiconductor wafers are processed in the same spatial sequence with respect to a global alignment feature of the semiconductor wafer. A balance mass is not needed to counteract the motion of a stage because the opposite motions of the respective stages cancel each other.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Fu LIN, Yung-Cheng CHEN, Heng-Jen LEE, Chin-Hsiang LIN
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Publication number: 20110076843Abstract: A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Hsiung Huang, Chin-Hsiang Lin, Heng-Jen Lee, Heng-Hsin Liu
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Patent number: 7901854Abstract: A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.Type: GrantFiled: May 8, 2009Date of Patent: March 8, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chang Huang, Heng-Hsin Liu, Heng-Jen Lee
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Publication number: 20110033787Abstract: A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count.Type: ApplicationFiled: August 7, 2009Publication date: February 10, 2011Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Wei Lin, Yung-Cheng Chen, Heng-Jen Lee
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Publication number: 20110024924Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yuan Shih, Sophia Wang, Heng-Hsin Liu, Heng-Jen Lee
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Publication number: 20100321660Abstract: An apparatus includes a radiation source that emits a radiation beam that causes substantially all of a quantity of material to evaporate; and structure having first and second surface portions, a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion, and a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion. A different aspect involves emitting a radiation beam toward a quantity of material, the radiation beam causing substantially all of the quantity of material to evaporate; operating a structure having first and second surface portions in a first operational mode wherein a greater quantity of a byproduct of the evaporation impinges on the first surface portion; and thereafter operating the structure in a second operational mode wherein a greater quantity of the byproduct impinges on the second surface portion.Type: ApplicationFiled: June 17, 2009Publication date: December 23, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Chun Peng, Heng-Jen Lee, Tung-Li Wu, I-Hsiung Huang
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Publication number: 20100308439Abstract: A dual wavelength exposure system provides for patterning a resist layer formed on a wafer for forming semiconductor devices, using two exposure operations, one including a first radiation having a first wavelength and the other including a second radiation including a second wavelength. Different or the same lithography tool may be used to generate the first and second radiation. For each die formed on the semiconductor device, a critical portion of the pattern is exposed using a first exposure operation that uses a first radiation with a first wavelength and a non-critical portion of the pattern is exposed using a second exposure operation utilizing the second radiation at a second wavelength. The resist material is chosen to be sensitive to both the first radiation having a first wavelength and the second radiation having the second wavelength.Type: ApplicationFiled: June 4, 2009Publication date: December 9, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Heng-Jen LEE, Jui-Chun PENG, I-Hsiung HUANG
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Publication number: 20100285399Abstract: A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.Type: ApplicationFiled: May 8, 2009Publication date: November 11, 2010Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chang Huang, Heng-Hsin Liu, Heng-Jen Lee
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Publication number: 20090258159Abstract: A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yih-Chen Su, Ting-Hao Hsu, Sheng-Chi Chin, Heng-Jen Lee, Hung Chang Hsieh, Yao-Ching Ku
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Publication number: 20090206057Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Hsiung Huang, Chi-Lun Lu, Heng-Jen Lee, Sheng-Chi Chin, Yao-Ching Ku
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Patent number: 7393616Abstract: A method including: providing collinear first and second lines in a mask layer over a substrate, the first line having at one end a first line end and having a first line body adjacent the first line end, and the second line having at one end a second line end and having a second line body adjacent the second line end; measuring line widths of the first line body and the second line body; locating effective line end positions for the first line end based on the line width of the first line body and for the second line end based on the line width of the second line body; and measuring a distance between the effective line end positions, as an effective line end spacing.Type: GrantFiled: April 4, 2006Date of Patent: July 1, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiann Yuan Huang, Anderson Chang, Chih-Ming Ke, Heng-Jen Lee, Chin-Hsiang Lin, Tsai-Sheng Gau
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Publication number: 20070264594Abstract: A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.Type: ApplicationFiled: May 9, 2007Publication date: November 15, 2007Inventors: Ching-Yu Chang, Heng-Jen Lee, Chin-Hsiang Lin, Hua-Tai Lin, Kuei Shun Chen, Bang-Chein Ho, Li-Kong Turn, Hung-Jui Kuo, Ko-Bin Kao, Tsung-Chih Chien