Abstract: Transparent conductive layers usable as ohmic contacts for III-V semiconductors with work functions between 4.1 and 4.7 eV are formed by annealing layers of transparent oxide with thin (0.1-5nm) layers of conductive metal. When the layers interdiffuse during the annealing, some of the conductive metal atoms remain free to reduce resistivity and others oxidize to reduce optical absorption. Examples of the transparent oxides include indium-tin oxide, zinc oxide, and aluminum zinc oxide with up to 5 wt % Al. Examples of the metals include aluminum and titanium. The work function of the transparent conductive layer can be tuned to match the contacted semiconductor by adjusting the ratio of metal to transparent oxide.

Abstract: Transparent ohmic contacts to p-GaN and other high-work-function (?4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.

Abstract: Transparent conductive layers usable as ohmic contacts for III-V semiconductors with work functions between 4.1 and 4.7 eV are formed by annealing layers of transparent oxide with thin (0.1-5 nm) layers of conductive metal. When the layers interdiffuse during the annealing, some of the conductive metal atoms remain free to reduce resistivity and others oxidize to reduce optical absorption. Examples of the transparent oxides include indium-tin oxide, zinc oxide, and aluminum zinc oxide with up to 5 wt % Al. Examples of the metals include aluminum and titanium. The work function of the transparent conductive layer can be tuned to match the contacted semiconductor by adjusting the ratio of metal to transparent oxide.

Abstract: A ternary transparent conductive oxide, indium zinc oxide (IZO), is formed as a thin film by co-sputtering zinc oxide with indium oxide at a deposition temperature between 25 and 200 C. Optionally, up to 1-2% Al may be added by various methods. The layers may be annealed at temperatures between 200 and 400 C. Measurements of IZO with 75-85 wt % In2O3 showed low resistivity and low visible absorbance, both of which were thermally stable up to 400 C.

Abstract: Transparent ohmic contacts to p-GaN and other high-work-function (?4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.

Abstract: Methods are used to develop and evaluate new materials and deposition processes for use as TCO materials in HJCS solar cells. The TCO layers allow improved control over the uniformity of the TCO conductivity and interface properties, and reduce the sensitivity to the texture of the wafer. In Some embodiments, the TCO materials include indium, zinc, tin, and aluminum.

Abstract: A method for preparing a bottle-shaped deep trench first forms a first mask with at least one opening on a substrate including a first epitaxy layer, an insulation layer on the first epitaxy layer and a second epitaxy layer on the insulation layer. A first etching process is performed to remove a portion of the substrate under the opening down to the interior of the insulation layer to form a trench, and a thermal treating process is then performed to form a second mask on the inner sidewall of the trench. Subsequently, a second etching process is performed to remove a portion of the substrate under the opening down to the interior of the first epitaxy layer to form a deep trench, and a third etching process is performed to remove a portion of the first epitaxy layer so as to form the bottle-shaped deep trench with an enlarged surface.

Abstract: The present gate structure comprises a gate oxide layer positioned on a substrate, a conductive stack positioned on the gate oxide layer, a passivation layer positioned on the sidewall of the conductive stack, and a cap layer positioned on the conductive stack. The conductive stack includes a polysilicon layer, a tungsten nitride layer, and a tungsten layer. The passivation layer can be made of silicon oxide, silicon nitride, or silicon oxynitride. The present method for preparing the gate structure comprises steps of forming a gate oxide layer, a conductive stack, and a cap layer on a semiconductor substrate in sequence, removing a portion of the gate oxide layer, the conductive stack, and the cap layer to form at least one opening, implanting silicon ions into the sidewall of the conductive stack, and performing a thermal treating process to transform the sidewall with silicon ions into a passivation layer.

Abstract: A method of controlling the implant dosage is provided. First, the residual gases within an ion implant station are analyzed and the partial pressure of each residual gas is measured. Thereafter, the current Im of the ion beam is measured and the real dosage Ir of the ion beam implanted into a wafer is calculated. Since all the residual gases in the ion implant station are considered, the implanting dosage can be accurately controlled.

Abstract: A method of controlling the implant dosage is provided. First, the residual gases within an ion implant station are analyzed and the partial pressure of each residual gas is measured. Thereafter, the current Im of the ion beam is measured and the real dosage Ir of the ion beam implanted into a wafer is calculated. Since all the residual gases in the ion implant station are considered, the implanting dosage can be accurately controlled.

Abstract: A method of prohibiting from producing a protrusion alongside a silicide layer of a gate unit is disclosed. The method includes steps of (a) providing a chamber and a semiconductor wafer having the gate unit thereon, (b) loading the semiconductor wafer into the chamber, (c) providing a mixing gas of nitrogen gas and hydrogen gas into the chamber and performing a rapid thermal anneal (RTA) step for the gate unit, and (d) performing a rapid thermal oxidation (RTO) step for the gate unit. Alternatively, the method includes steps of (a) providing a first chamber and a semiconductor wafer having a gate unit thereon, (b) loading the semiconductor wafer into the first chamber and purging oxygen gas therein, (c) performing a rapid thermal anneal (RTA) step for the gate unit, and (d) performing a rapid thermal oxidation (RTO) step for the gate unit.