Patents by Inventor Heng Keong Yip
Heng Keong Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11329030Abstract: A method of producing a chip module includes providing a carrier; arranging semiconductor chips on the carrier; applying an electrically insulating material on the carrier; and structuring the carrier such that the chip module is provided, wherein the chip module includes separate carrier sections produced by structuring the carrier, the carrier sections of the chip module connected by the electrically insulating material.Type: GrantFiled: May 2, 2017Date of Patent: May 10, 2022Assignee: OSRAM Opto Semiconductors GmbHInventor: Heng Keong Yip
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Publication number: 20200083200Abstract: A method of producing a chip module includes providing a carrier; arranging semiconductor chips on the carrier; applying an electrically insulating material on the carrier; and structuring the carrier such that the chip module is provided, wherein the chip module includes separate carrier sections produced by structuring the carrier, the carrier sections of the chip module connected by the electrically insulating material.Type: ApplicationFiled: May 2, 2017Publication date: March 12, 2020Inventor: Heng Keong Yip
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Patent number: 9331046Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: GrantFiled: June 26, 2014Date of Patent: May 3, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Chu-Chung Lee, Kian Leong Chin, Kevin J. Hess, James Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
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Publication number: 20140308779Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: ApplicationFiled: June 26, 2014Publication date: October 16, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Chu-Chung LEE, Kian Leong CHIN, Kevin J. HESS, Patrick P. JOHNSTON, Tu-Anh N. TRAN, Heng Keong YIP
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Patent number: 8791582Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: GrantFiled: July 28, 2010Date of Patent: July 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Chu-Chung Lee, Kian Leong Chin, Kevin J. Hess, Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
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Patent number: 8643172Abstract: A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader is generally T-shaped in cross-section. The top portion has a hole at its center that extends from a top surface of the top portion to the at least one channel of the base portion. Mold compound is injected through the hole and out through the channels.Type: GrantFiled: June 8, 2007Date of Patent: February 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Chee Seng Foong, Aminuddin Ismail, Heng Keong Yip
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Publication number: 20120025401Abstract: An integrated circuit package includes a semiconductor die attached to a package support. The die has a plurality of peripheral bond pads along a periphery of the die and a first bond pad on an interior portion of the die wherein the first bond pad is a power supply bond pad. A conductive distributor is over the die and within a perimeter of the die and has a first opening. The plurality of bond pads are located between the perimeter of the die and a perimeter of the conductive distributor. The first bond pad is in the first opening. A first bond wire is connected between the first bond pad and the conductive distributor. A second bond wire is connected between a first peripheral bond pad of the plurality of peripheral bond pads and the conductive distributor.Type: ApplicationFiled: July 28, 2010Publication date: February 2, 2012Inventors: CHU-CHUNG LEE, Kian Leong Chin, Kevin J. Hess, Patrick Johnston, Tu-Anh N. Tran, Heng Keong Yip
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Patent number: 7955953Abstract: A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer.Type: GrantFiled: December 17, 2007Date of Patent: June 7, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Heng Keong Yip
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Patent number: 7741196Abstract: A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.Type: GrantFiled: January 29, 2007Date of Patent: June 22, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Heng Keong Yip, Wai Yew Lo, Lan Chu Tan
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Patent number: 7566648Abstract: A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A second etching operation is performed on the metal layer to form the solder pad. A solder mask is formed on the substrate and a portion of the solder pad.Type: GrantFiled: April 22, 2007Date of Patent: July 28, 2009Assignee: Freescale Semiconductor Inc.Inventors: Heng Keong Yip, Thoon Khin Chang, Chee Seng Foong
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Publication number: 20090152717Abstract: A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer.Type: ApplicationFiled: December 17, 2007Publication date: June 18, 2009Inventors: Wai Yew Lo, Heng Keong Yip
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Patent number: 7531383Abstract: An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.Type: GrantFiled: October 31, 2006Date of Patent: May 12, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Heng Keong Yip
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Patent number: 7494924Abstract: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.Type: GrantFiled: March 6, 2006Date of Patent: February 24, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, On Lok Chau, Gor Amie Lai, Heng Keong Yip, Thoon Khin Chang, Lan Chu Tan
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Patent number: 7473586Abstract: A flip-chip bump carrier type package is formed by providing a sheet of metal foil and forming cavities in a first surface of the sheet. The cavities are plated with a conductive metal to form external interconnects. An insulating film is formed over the metal foil first surface and the plated cavities and then vias are formed in the insulating film. The vias contact respective ones of the plated cavities. The vias are then plated and a solder resist film is formed over the insulating film and the plated vias. The solder resist film is processed to form exposed areas above the vias, which areas are then plated with a conductive metal. A bumped semiconductor die is attached to the first surface of the metal foil, where the die bumps contact respective ones of the plated, exposed areas, which electrically connects the die to the plated cavities. Finally, the sheet of metal foil is removed so that outer surfaces of the plated cavities are exposed.Type: GrantFiled: September 3, 2007Date of Patent: January 6, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Wai Yew Lo, Heng Keong Yip
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Publication number: 20080305584Abstract: A heat spreader for an integrated circuit has a base portion and a top portion. The base portion is attachable to a surface of the integrated circuit, and has at least one channel extending therethrough. The top portion that is larger than the base portion such that the heat spreader is generally T-shaped in cross-section. The top portion has a hole at its center that extends from a top surface of the top portion to the at least one channel of the base portion. Mold compound is injected through the hole and out through the channels.Type: ApplicationFiled: June 8, 2007Publication date: December 11, 2008Inventors: Chee Seng Foong, Aminuddin Ismail, Heng Keong Yip
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Publication number: 20080258297Abstract: A method of making a solder pad includes providing a substrate having a metal layer formed on it, and applying a photo resist to the metal layer. The photo resist is patterned. A first etching operation is performed on the metal layer to form voids in the metal layer. A second etching operation is performed on the metal layer to form the solder pad. A solder mask is formed on the substrate and a portion of the solder pad.Type: ApplicationFiled: April 22, 2007Publication date: October 23, 2008Inventors: Heng Keong YIP, Thoon Khin Chang, Chee Seng Foong
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Publication number: 20080179710Abstract: A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.Type: ApplicationFiled: January 29, 2007Publication date: July 31, 2008Inventors: Heng Keong Yip, Wai Yew Lo, Lan Chu Tan
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Publication number: 20080182120Abstract: A bond pad (12, 14) for a semiconductor device (10) is generally L-shaped and includes a first portion (20, 24) for receiving a bond wire, and a second portion (22, 26) extending substantially perpendicularly from the first portion (20, 24). The bond pad (12) may include a third portion (16, 18) adjacent to the first portion (20). The third portion (16, 18) may be an embedded power pad (16) or an embedded ground pad (18).Type: ApplicationFiled: January 28, 2007Publication date: July 31, 2008Inventors: Lan Chu Tan, Heng Keong Yip, Cheng Choi Yong
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Patent number: 7384819Abstract: A method of forming a semiconductor package (50 and 52) includes providing a substrate (14) having a die pad and bond pads on a first surface (20) and conductive pads (66, 68 and 74) on a second surface (22). An integrated circuit (IC) die (38) is attached to the die pad and the first surface (20) of the substrate (14) is attached to a lead frame (26). The substrate (14) is electrically connected to the lead frame (26), and the IC die (38) is electrically connected to the substrate (14) and the lead frame (26). The IC die (14), the electrical connections (40, 42 and 44), a portion of the substrate (14) and a portion of the lead frame (26) are encapsulated with a mold compound (46), forming a stackable package (48). The conductive pads (66, 68 and 74) on the second surface (22) of the substrate (14) are not encapsulated by the mold compound (46).Type: GrantFiled: April 28, 2006Date of Patent: June 10, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Heng Keong Yip, Lan Chu Tan
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Publication number: 20080099784Abstract: An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.Type: ApplicationFiled: October 31, 2006Publication date: May 1, 2008Inventors: Wai Yew Lo, Heng Keong Yip