Abstract: A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region. The matrix electrode comprises a plurality of first electrodes arranged on the epitaxial stack, a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes, a plurality of third electrodes arranged adjacent to the plurality of first electrodes and second electrodes. One of the plurality of first electrodes comprises a first side, a second side, a third side and a fourth side. The first side and the third side are opposite sides, and the second side and the fourth side are opposite sides. Two of the plurality of second electrodes are arranged on the first side and the third side, and two of the plurality of third electrodes are arranged on the second side and the fourth side.

Abstract: A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region. The matrix electrode comprises a plurality of first electrodes arranged on the epitaxial stack, a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes, a plurality of third electrodes arranged adjacent to the plurality of first electrodes and second electrodes. One of the plurality of first electrodes comprises a first side, a second side, a third side and a fourth side. The first side and the third side are opposite sides, and the second side and the fourth side are opposite sides. Two of the plurality of second electrodes are arranged on the first side and the third side, and two of the plurality of third electrodes are arranged on the second side and the fourth side.

Abstract: A field effect transistor includes a substrate; a first semiconductor layer, disposed over the substrate; a second semiconductor layer, disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas; a p+ III-V semiconductor layer, disposed over the second semiconductor layer; and a depolarization layer, disposed between the second semiconductor layer and the p+ III-V semiconductor layer, wherein the depolarization layer includes a metal oxide layer.

Abstract: A semiconductor power device, comprising: a substrate; a first semiconductor layer with a first lattice constant formed on the substrate; a first grading layer formed on the first semiconductor layer and comprising a first portion; a second grading layer formed on the first grading layer; a second semiconductor layer with a second lattice constant formed on the second grading layer; a first interlayer formed in the first grading layer and adjacent to the first portion of the first grading layer; and a second interlayer formed in the second grading layer; wherein the first interlayer comprises a first superlattice including a series of Alx1Ga1-x1N/Aly1Ga1-y1N alternate layers, (x1-y1)?0.2, and the second interlayer comprises a second superlattice including a series of Alx2Ga1-x2N/Aly2Ga1-y2N alternate layers, (x2-y2)?0.2, wherein the average of x1 and y1 is larger than that of x2 and y2.

Abstract: A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region, and a plurality of first bridges electrically connecting the plurality of second electrodes. The matrix electrode structure comprises a plurality of first electrodes arranged on the epitaxial stack and a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes. One of the bridges is arranged between two of the second electrodes and crossed over one of the first electrodes.

Abstract: The present application discloses a semiconductor device comprising a crystalline substrate having a first region and a second region, a nuclei structure on the first region, a first crystalline buffer layer on the nuclei structure, a void between the second region and the first crystalline buffer layer, a second crystalline buffer layer on the first crystalline buffer layer, an intermediate layer located between the first crystalline buffer layer and the second crystalline buffer layer, and a semiconductor device layer on the second crystalline buffer layer.

Abstract: A FET disclosed herein comprises a substrate, a first semiconductor layer disposed over the substrate, a second semiconductor layer disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas. The E-mode FET further comprises a p+ III-V semiconductor layer disposed over the second semiconductor layer and a depolarization layer disposed between the second semiconductor layer and the p+ III-V semiconductor layer.

Abstract: This disclosure discloses a power device. The power device comprises a substrate; a first semiconductor layer having a first band gap and disposed on the substrate; a second semiconductor layer having a second band gap being lager than the first band gap and disposed on the first semiconductor layer; a third semiconductor layer having a third band gap smaller than the second band gap layer and disposed on the second semiconductor layer; a source electrode disposed on the third semiconductor layer; a base electrode electrically connecting the source electrode; and a p-type metal-oxide layer disposed between the base electrode and the third semiconductor layer.

Abstract: A power device disclosed herein comprises a substrate, a first semiconductor layer formed on the substrate, a second semiconductor layer formed on the first semiconductor layer and comprising a first element of group III, a third semiconductor layer formed on the second semiconductor layer and a plurality of first interlayers formed in the third semiconductor layer and comprising a second element of III group. The first element of III group and the second element of III group are the same. The second semiconductor layer and the plurality of first interlayers are doped with carbon.

Abstract: A high electron mobility transistor comprises a substrate, an epitaxial stack arranged above the substrate and having a first region and a second region surrounding the first region, a matrix electrode structure arranged in the first region, and a plurality of first bridges electrically connecting the plurality of second electrodes. The matrix electrode structure comprises a plurality of first electrodes arranged on the epitaxial stack and a plurality of second electrodes arranged on the epitaxial stack and adjacent to the plurality of first electrodes. One of the bridges is arranged between two of the second electrodes and crossed over one of the first electrodes.

Abstract: A semiconductor power device, comprising: a substrate; a first semiconductor layer with a first lattice constant formed on the substrate, wherein the first semiconductor layer comprises a first group III element; a first grading layer formed on the first semiconductor layer and comprising a first portion; a second semiconductor layer with a second lattice constant formed on the first grading layer, wherein the second semiconductor layer comprises a second group III element; and a first interlayer formed in the first grading layer and adjacent to the first portion of the first grading layer, wherein a composition of the first interlayer is different from that of the first portion, and the first grading layer comprises the first group III element and the second group III element, and concentrations of both the first group III element and the second group III element in the first grading layer are gradually changed.

Abstract: A FET disclosed herein comprises a substrate, a first semiconductor layer disposed over the substrate, a second semiconductor layer disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas. The E-mode FET further comprises a p+ III-V semiconductor layer disposed over the second semiconductor layer and a depolarization layer disposed between the second semiconductor layer and the p+ III-V semiconductor layer.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract: The advantage of narrow-bandgap Sb-based devices is the realization of high-frequency operation with much lower power consumption. However, some properties such as chemical stability are the key issues for developing Sb-based devices. The process temperature of the ion implant and thermal annealing in conventional silicon industry is over 1000° C. Sb-based materials are easily degraded at temperature greater 300° C. Thus, this invention provides three processes for self-aligned gate with lower process temperature (<300° C.) to reduce device access region resistance and maintain material quality.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract: The invention provides two Sb-based n- or p-channel layer structures as a template for MISFET and complementary MISFET development. Four types of MISFET devices and two types of complementary MISFET circuit devices can be developed based on the invented layer structures. Also, the layer structures can accommodate more than one complementary MISFETs and more than one single active MISFETs to be integrated on the same substrate monolithically.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract: An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer.

Abstract: An epitaxial layers structure and a method for fabricating HBTs and HEMTs on a common substrate are disclosed. The epitaxial layers comprise generally a set of HBT layers on the top of a set of HEMT layers. The method can be used to fabricate HBT, E-mode HEMT and D-mode HEMT as well as passive devices, that enabling monolithic integration of a significant number of devices on a common substrate by a cost-effective way.