Abstract: A MAC architecture for WLAN stations partitions functionality between a software-based MAC component and a hardware-based MAC component that work together to balance function and performance. In general, the fulcrum for this balance centers on timing requirements. Accordingly, the hardware-based MAC component is designed to handle many of the functions that are processor-intensive and/or must be performed under strict timing constraints. The software-based MAC component is designed to handle many of the functions that are memory-intensive, but present more lenient timing requirements. The software-based MAC component may be configured to provide an efficient and robust interface to the hardware-based MAC component. In particular, the software-based MAC component may format and prioritize packets to be sent over the air interface, and generate a command structure that provides instructions for the hardware-based MAC component to process the packet.

Abstract: A MAC architecture for WLAN stations partitions functionality between a software-based MAC component and a hardware-based MAC component that work together to balance function and performance. In general, the fulcrum for this balance centers on timing requirements. Accordingly, the hardware-based MAC component is designed to handle many of the functions that are processor-intensive and/or must be performed under strict timing constraints. The software-based MAC component is designed to handle many of the functions that are memory-intensive, but present more lenient timing requirements. The software-based MAC component may be configured to provide an efficient and robust interface to the hardware-based MAC component. In particular, the software-based MAC component may format and prioritize packets to be sent over the air interface, and generate a command structure that provides instructions for the hardware-based MAC component to process the packet.

Abstract: An improved binary tree and decoder are disclosed wherein all the codewords are moved to one side of a binary tree. A compressed bit stream is fed to a decoder. The decoder uses a parser, an address generator, and the binary tree to determine the codewords contained in the compressed bit stream. The decoder examines the variable length encoded bits and compares them with the binary tree at each level to determine if the codeword is complete. The parser detects the end of the codeword and generates an offset for the address generator. The address generator uses the binary tree and offset to generate a block address for each unique codeword. The block address is then used to output uncompressed data from a pattern look up table.

Abstract: A high access speed memory for the internal storage of data and the addressable input/output transfer of data thereto, the memory comprising means for the dynamic storage of data, means for the static storage of data, and means for transferring data between the dynamic storage means and the static storage means. The intimate interfacing of the static and dynamic memories provides a high access speed pathway to the dynamically stored data while impacting minimally on sense amplification timing and the use of a redundant dynamic memory scheme.