Patents by Inventor Heng Shen
Heng Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133514Abstract: A frame device includes a back board, a buckle member and a casing. The back board has a groove. The buckle member is disposed on the back board, and has a first part member and the second part member disposed corresponding to the groove, and a distance between the first part member and the second part member varies along a direction. The casing is provided with a hook having a first engaging part and a second engaging part, and a distance between the first engaging part and the second engaging part varies along the direction. The first part member is engaged with the first engaging part, and the second part member is engaged with the second engaging part.Type: ApplicationFiled: September 21, 2023Publication date: April 25, 2024Inventors: Heng-Shen KUO, Yung-Shen HUANG, I-Han LIU
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Publication number: 20240128184Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a redistribution layer, an electronic unit, and a conductive bump. The redistribution layer includes a first seed layer, a first conductive layer, and a first insulating layer. The first conductive layer is disposed on the first seed layer, the first insulating layer is disposed on the first conductive layer, and an opening of the first insulating layer exposes at least a portion of the first conductive layer. The electronic unit is electrically connected to the redistribution layer. The conductive bump is disposed between the first conductive layer and the electronic unit and is correspondingly disposed in the opening. The electronic unit is electrically connected to the redistribution layer via the conductive bump. The conductive bump is directly in contact with the first conductive layer.Type: ApplicationFiled: December 6, 2022Publication date: April 18, 2024Applicant: Innolux CorporationInventors: Ker-Yih Kao, Chin-Ming Huang, Heng-Shen Yeh
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Patent number: 11962301Abstract: Technologies for low jitter and low power ring oscillators with multi-phase signal reassembly are described. A ring oscillator circuit includes a ring oscillator with a set of M delay stages, each stage outputs a phase signal, where M is a positive integer greater than one. The ring oscillator circuit includes a phase selector circuit coupled to the ring oscillator. The phase selector circuit can receive M phase signals from the ring oscillator and generate N phase signals based on the M phase signals, where N is a positive integer less than M.Type: GrantFiled: August 18, 2022Date of Patent: April 16, 2024Assignee: Nvidia CorporationInventors: Chun-Ju Shen, Chien-Heng Wong, Ying Wei
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Publication number: 20240058713Abstract: An interactive toy system is shown and described. The toy system includes a double walled flask adapted to be connected to a base forming an internal space capable of holding an object or a figurine. When an empty space between the double walls is filled with an opaque fluid, it gives the player the impression that the whole flask is filled with such fluid. The toy system includes a smoke generating system, light emitting LEDs and a speaker. During the controlled play process, ingredients are added to an isolated fluid chamber on top of the flask. The operation and the special effects from the smoke, the sound, the light, and the phenomenon in the fluid chamber gives the impression that the creature is being created inside the opaque flask. When the process is concluded and the fluid in the flask is drained, the figurine inside the flask is revealed.Type: ApplicationFiled: August 14, 2023Publication date: February 22, 2024Inventors: Alex Martin, James Austin-Smith, Brandon Cole Sopinsky, Miguel Rusch, Heng Shen Yeap
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Publication number: 20230402292Abstract: A method of manufacturing an electronic device includes providing a substrate, providing an intermediate layer on the substrate, and providing an isolation layer on the intermediate layer. The substrate includes an active region and a peripheral region. The peripheral region is adjacent to the active region, and the ratio of the area of the active region to the area of the substrate surface is between 75% and 92%. The isolation layer includes a first surface and at least one slope. The first surface of the isolation layer is correspondingly disposed in the active region. The at least one slope of the isolation layer is correspondingly disposed in the peripheral region and at a first angle with respect to the substrate surface.Type: ApplicationFiled: June 27, 2022Publication date: December 14, 2023Applicant: InnoLux CorporationInventors: Chuan-Ming YEH, Heng-Shen YEH, Sheng-Hui CHIU, Kuo-Jung FAN
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Publication number: 20230377904Abstract: The embodiment of the disclosure provides a composite layer circuit element of an electronic device. The composite layer circuit element includes a first dielectric layer, a first circuit layer and a second dielectric layer. The first circuit layer is disposed on the first dielectric layer, and the second dielectric layer is disposed on the first circuit layer. A thickness of the first dielectric layer is greater than a thickness of the second dielectric layer in a cross section view.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Applicant: Innolux CorporationInventors: Chuan-Ming Yeh, Heng-Shen Yeh, Kuo-Jung Fan, Cheng-Chi Wang
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Patent number: 11764077Abstract: The embodiment of the disclosure provides a composite layer circuit element and a manufacturing method thereof. The manufacturing method of the composite layer circuit element includes the following. A carrier is provided. A first dielectric layer is formed on the carrier, and the first dielectric layer is patterned. The carrier on which the first dielectric layer is formed is disposed on a first curved-surface mold, and the first dielectric layer is cured. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned. The carrier on which the first dielectric layer and the second dielectric layer are formed is disposed on a second curved-surface mold, and the second dielectric layer is cured. A thickness of a projection of the first curved-surface mold is smaller than a thickness of a projection of the second curved-surface mold.Type: GrantFiled: November 11, 2021Date of Patent: September 19, 2023Assignee: Innolux CorporationInventors: Chuan-Ming Yeh, Heng-Shen Yeh, Kuo-Jung Fan, Cheng-Chi Wang
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Publication number: 20230238278Abstract: A manufacturing method of a package structure of an electronic device, including the following steps, is provided. A first seed layer is formed on a carrier plate. A first metal layer is formed on the first seed layer. A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. A first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. After performing the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer, and the first insulating layer is placed in a microenvironment controlling box. After taking the carrier plate out of the microenvironment controlling box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.Type: ApplicationFiled: May 18, 2022Publication date: July 27, 2023Applicant: Innolux CorporationInventors: Ching-Wei Chen, Yu-Jen Chang, Tzu-Yen Chiu, Hung-I Tseng, Chuan-Ming Yeh, Heng-Shen Yeh
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Publication number: 20230026151Abstract: The embodiment of the disclosure provides a composite layer circuit element and a manufacturing method thereof. The manufacturing method of the composite layer circuit element includes the following. A carrier is provided. A first dielectric layer is formed on the carrier, and the first dielectric layer is patterned. The carrier on which the first dielectric layer is formed is disposed on a first curved-surface mold, and the first dielectric layer is cured. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned. The carrier on which the first dielectric layer and the second dielectric layer are formed is disposed on a second curved-surface mold, and the second dielectric layer is cured. A thickness of a projection of the first curved-surface mold is smaller than a thickness of a projection of the second curved-surface mold.Type: ApplicationFiled: November 11, 2021Publication date: January 26, 2023Applicant: Innolux CorporationInventors: Chuan-Ming Yeh, Heng-Shen Yeh, Kuo-Jung Fan, Cheng-Chi Wang
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Publication number: 20220189863Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer, a first dielectric layer disposed on the first metal layer, a second metal layer disposed on the first dielectric layer, and a second dielectric layer disposed on the second metal layer. A coefficient of thermal expansion of the first dielectric layer is less than a coefficient of thermal expansion of the second dielectric layer.Type: ApplicationFiled: November 21, 2021Publication date: June 16, 2022Applicant: Innolux CorporationInventors: Hung-Sheng Chou, Wen-Hsiang Liao, Kuo-Jung Fan, Heng-Shen Yeh, Cheng-Chi Wang
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Publication number: 20220189862Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer and a first dielectric layer disposed on the first metal layer. A range of a difference between a coefficient of thermal expansion of the first dielectric layer and a coefficient of thermal expansion of the first metal layer is 0% to 70% of the coefficient of thermal expansion of the first dielectric layer.Type: ApplicationFiled: November 18, 2021Publication date: June 16, 2022Applicant: Innolux CorporationInventors: Hung-Sheng Chou, Wen-Hsiang Liao, Kuo-Jung Fan, Heng-Shen Yeh, Cheng-Chi Wang
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Publication number: 20220181242Abstract: A redistribution layer structure and the manufacturing method thereof are provided. The redistribution layer structure includes a first metal layer, a first dielectric layer, a second metal layer, and a second dielectric layer. The first dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the second metal layer. A chemical resistance of the first dielectric layer is greater than a chemical resistance of the second dielectric layer.Type: ApplicationFiled: November 22, 2021Publication date: June 9, 2022Applicant: Innolux CorporationInventors: Kuo-Jung Fan, Cheng-Chi Wang, Heng-Shen Yeh, Chuan-Ming Yeh
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Patent number: 11299569Abstract: The present invention provides a composition for 3D printing, a process for preparing the same and an article thereof. By the solidifying method of UV irradiation, 3D printing is implemented. During said implementation, there is no need of high temperature heating, thus energy consumption is reduced, and there is no need for special solvent, thus harm to the environment is reduced. Meanwhile, the present invention uses micro-nano powder as the main material and polymer resin as adhesive, and at the same time, adds irradiation sensitizer. After electron beam irradiation, the polymer resin forms three-dimensional crosslinked network, thereby the strength, heat resistance and chemical resistance are improved after resin adhesion.Type: GrantFiled: April 24, 2015Date of Patent: April 12, 2022Assignee: INSTITUTE OF CHEMISTRY, CHINESE ACADEMY OF SCIENCESInventors: Heng Shen, Jing Guo, Tang Zhu, Ning Zhao, Jian Xu, Wenhua Sun, Jinyong Dong, Chuncheng Li, Wenxin Fu, Xuechun Lin, Yongmei Ma
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Patent number: 11233121Abstract: A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5×1012 ions/cm3 to about 5×1013 ions/cm3, and the lightly doped peripheral region has a same maximum depth as the highly doped central region.Type: GrantFiled: June 15, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Hsiung Yang, Long-Shih Lin, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu
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Patent number: 10840371Abstract: The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.Type: GrantFiled: October 25, 2019Date of Patent: November 17, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Feng Yang, Chih-Heng Shen, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang
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Publication number: 20200312957Abstract: A bipolar transistor includes a substrate having a first well with a first dopant type; and a split collector region in the substrate, the split collector region including a highly doped central region having the first dopant type, and a lightly doped peripheral region having a second dopant type, opposite the first dopant type, wherein the lightly doped peripheral region surrounds the highly doped central region, a dopant concentration of the lightly doped peripheral region ranges from about 5×1012 ions/cm3 to about 5×1013 ions/cm3, and the lightly doped peripheral region has a same maximum depth as the highly doped central region.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Inventors: Fu-Hsiung YANG, Long-Shih LIN, Kun-Ming HUANG, Chih-Heng SHEN, Po-Tao CHU
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Patent number: 10686036Abstract: A method of making a bipolar transistor includes patterning a first photoresist over a collector region of the bipolar transistor, the first photoresist defining a first opening. The method further includes performing a first implantation process through the first opening. The method further includes patterning a second photoresist over the collector region, the second photoresist defining a second opening different from the first opening. The method further includes performing a second implantation process through the second opening, wherein a dopant concentration resulting from the second implantation process is different from a dopant concentration resulting from the first implantation process.Type: GrantFiled: May 4, 2017Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Hsiung Yang, Long-Shih Lin, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu
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Publication number: 20200066902Abstract: The method comprises forming a drain region in the first layer. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer.Type: ApplicationFiled: October 25, 2019Publication date: February 27, 2020Inventors: Tsai-Feng YANG, Chih-Heng SHEN, Chun-Yi YANG, Kun-Ming HUANG, Po-Tao CHU, Shen-Ping WANG
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Patent number: 10461183Abstract: A device having a drain region with a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region spaced from and surrounding the drain region in the first layer.Type: GrantFiled: January 29, 2018Date of Patent: October 29, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsai-Feng Yang, Chih-Heng Shen, Chun-Yi Yang, Kun-Ming Huang, Po-Tao Chu, Shen-Ping Wang
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Publication number: 20180151724Abstract: A device having a drain region with a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region spaced from and surrounding the drain region in the first layer.Type: ApplicationFiled: January 29, 2018Publication date: May 31, 2018Inventors: Tsai-Feng YANG, Chih-Heng SHEN, Chun-Yi YANG, Kun-Ming HUANG, Po-Tao CHU, Shen-Ping WANG