Abstract: A serial isolated communication method, applied to a transmitter of a serial isolated communication system, includes: obtaining isolated communication data to be transferred; encoding isolated communication data with more than two bits into corresponding data pulse signals according to a preset encoding rule, wherein a group of data pulse signals include a positive pulse, a negative pulse, and a delay of 0 or N pulse widths between the positive pulse and the negative pulse, and N?1; and transferring the data pulse signals to a receiver. A serial isolated communication method, applied to a receiver of a serial isolated communication system, includes: receiving data pulse signals transferred from a transmitter; decoding the data pulse signals into the isolated communication data according to a preset decoding rule; and obtaining the isolated communication data. Serial isolated communication device and system are further provided.

Abstract: A serial isolated communication method, applied to a transmitter of a serial isolated communication system, includes: obtaining isolated communication data to be transferred; encoding isolated communication data with more than two bits into corresponding data pulse signals according to a preset encoding rule, wherein a group of data pulse signals include a positive pulse, a negative pulse, and a delay of 0 or N pulse widths between the positive pulse and the negative pulse, and N?1; and transferring the data pulse signals to a receiver. A serial isolated communication method, applied to a receiver of a serial isolated communication system, includes: receiving data pulse signals transferred from a transmitter; decoding the data pulse signals into the isolated communication data according to a preset decoding rule; and obtaining the isolated communication data. Serial isolated communication device and system are further provided.

Abstract: A signal transmitting circuit and a signal receiving circuit for serial communication, and an electronic device are provided. The signal transmitting circuit includes a control module, a first transmitter, a second transmitter, a first differential pin, and a second differential pin, wherein the control module is configured to control the first transmitter to output a first signal via the first differential pin, and control the second transmitter to output a second signal via the second differential pin to record target information with a target signal after differentiating between the first signal and the second signal; and wherein if the target information includes data information and instant information, the data information is recorded in the target signal with a third signal with a first frequency while recording the instant information with a fourth signal with a second frequency, the first frequency is different from the second frequency.

Abstract: A transistor switching circuit and an integrated circuit thereof are provided. The transistor switching circuit includes: at least two transistors M1 and M2, and a voltage follower. The gate of the transistor M1 and the gate of the transistor M2 are connected to a first node G, the first node G is connected to a first current source, and the source of the transistor M1 and the source of the transistor M2 are connected to a second node S1. The voltage follower includes a transistor M3 and a second current source. The gate of the transistor M3 is connected to the second node S1, and the source of the transistor M3 is connected to the second current source. One end of a resistive device is connected to the source of the transistor M3, and another end of the resistive device is connected to the first node G.

Abstract: A signal transmitting circuit and a signal receiving circuit for serial communication, and an electronic device are provided. The signal transmitting circuit includes a control module, a first transmitter, a second transmitter, a first differential pin, and a second differential pin, wherein the control module is configured to control the first transmitter to output a first signal via the first differential pin, and control the second transmitter to output a second signal via the second differential pin to record target information with a target signal after differentiating between the first signal and the second signal; and wherein if the target information includes data information and instant information, the data information is recorded in the target signal with a third signal with a first frequency while recording the instant information with a fourth signal with a second frequency, the first frequency is different from the second frequency.

Abstract: A single stage current sense amplifier is described that generates a differential output that is proportional to a current through a sense resistor. The voltage across the sense resistor is Vsense. The current sense amplifier includes a differential transconductance amplifier having high impedance input terminals. An on-chip RC filter filters transients in the Vsense signal. A feedback circuit for each leg of the amplifier causes a pair of input transistors to conduct a fixed constant current irrespective of Vsense, which stabilizes the transconductance. A gain control resistor (Re) is coupled across terminals of the pair of input transistors and has Vsense across it. The current through the gain control resistor is therefore Vsensex1/Re. A level shifting circuit coupled to each of the input transistors lowers a common mode voltage at an output of the amplifier. Chopper circuits at the input and output cancel any offset voltages.

Abstract: A single stage current sense amplifier is described that generates a differential output that is proportional to a current through a sense resistor. The voltage across the sense resistor is Vsense. The current sense amplifier includes a differential transconductance amplifier having high impedance input terminals. An on-chip RC filter filters transients in the Vsense signal. A feedback circuit for each leg of the amplifier causes a pair of input transistors to conduct a fixed constant current irrespective of Vsense, which stabilizes the transconductance. A gain control resistor (Re) is coupled across terminals of the pair of input transistors and has Vsense across it. The current through the gain control resistor is therefore Vsensex1/Re. A level shifting circuit coupled to each of the input transistors lowers a common mode voltage at an output of the amplifier. Chopper circuits at the input and output cancel any offset voltages.

Abstract: An operational amplifier circuit includes an input differential circuit and a trim circuit for sensing the operational amplifier's input common mode voltage and generating an offset correction voltage in response thereto. The trim circuit reduces the amplifier's offset voltage dependence on input common mode voltage, and hence improves the common mode rejection ratio of the operational amplifier circuit.

Abstract: A folded cascode amplifier having improved slew comprises an input differential transistor pair circuit, a cascode branch circuit coupled to the differential pair circuit, and a boost circuit for increasing branch current when the amplifier is in a slew condition. The additional current increases slew of the amplifier without negatively affecting amplifier characteristics.

Abstract: Voltage offset of an integrated circuit amplifier is accurately determined for calibration of the device. Circuit connections are established between the integrated circuit and an external device, such as an IC handler. Internal noise gain resistors formed within the integrated circuit are connected by internal switches to the amplifier and the output voltage is measured so that a value of a voltage offset of the amplifier while the noise gain resistors are connected can be calculated. The use of internal noise gain resistors produces a voltage offset component of the output voltage that is significantly greater in magnitude than effects of thermocouple voltages generated by circuit junction connections.