Abstract: A semiconductor device is provided and includes a first substrate including a first transistor; a laser reflection layer on the first transistor; and a second substrate on the laser reflection layer, the second substrate including a second transistor.

Abstract: A camera module and array camera module with circuit board unit and photosensitive unit and manufacturing method thereof is provided. The array camera module includes two or more camera lenses and a circuit unit. The circuit unit includes a circuit board portion for electrically connecting two or more photosensitive sensors of the array camera module, and a conjoined encapsulation portion integrally encapsulated on the circuit board portion. The camera lenses are respectively arranged along the photosensitive paths of the photosensitive sensors.

Abstract: Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Abstract: A method of generating randomness by public participation may comprise: communicating with the commodity devices to execute a protocol comprising a setup phase, a contribution phase and a result-generation phase, wherein: in the setup phase, parameters are initialized, a verifiable delay function is setup, and the parameters are published; the contribution phase is divided into at least one first stage, published parameters are provided, random values are received, and a Merkle tree root and Merkle tree audit paths are published in each of the first stage; and the result-generation phase is divided into at least one second stage of the same number as that of the first stage, each second stage is dedicated to one of the first stage ahead of the second stage for a period, and in each second stage, computation is performed to generate a result of randomness which is published.

Abstract: A micro light-emitting diode includes a first stacked layer, a second stacked layer, a third stacked layer, a bonding layer, at least one etch stop layer, and a plurality of electrodes. The second stacked layer is disposed between the first stacked layer and the third stacked layer. The first stacked layer includes a first active layer. The second stacked layer includes a second active layer. The third stacked layer includes a third active layer. The bonding layer is disposed between the second stacked layer and the third stacked layer. The at least one etch stop layer is at least disposed between the first active layer and the second active layer. The plurality of electrodes are respectively electrically connected with the first stacked layer, the second stacked layer, and the third stacked layer. At least one electrode of the plurality of electrodes contacts the etch stop layer.

Abstract: Provided herein are methods of determining binding kinetics of a ligand. In some embodiments, the methods include contacting the ligand with a first surface of a substrate, which first surface comprises an electrically conductive coating and a population of virions connected to the first surface via one or more linker moieties, wherein viral envelopes of the virions display one or more proteins that bind, or are capable of binding, to the ligand, applying an alternating current electric field to the substrate to induce the virions to oscillate proximal to the first surface of the substrate, and detecting changes in oscillation amplitudes of the virions over a duration. Related virion oscillator array devices, systems and computer readable media are also provided.

Abstract: A hardware-in-loop simulation experiment platform of multiple input and multiple output loop control for MSWI process includes a real equipment layer and a virtual object layer, where in the real equipment layer and the virtual object layer realize communication through hard wirings and data acquisition cards, the real equipment layer and virtual object layer realize communication in OPC mode through Ethernet; the real equipment layer comprises monitoring equipment and control equipment, and the virtual object layer comprises an MSWI actuator model, an MSWI instrument device model and an MSWI process object model which are respectively operated in different industrial personal computers. The hardware-in-loop simulation experiment platform of multiple input and multiple output loop control for MSWI process provided by the invention is used for providing a reliable engineering verification environment for MSWI process control.

Abstract: One example embodiment provides one or more of: measuring, via a user equipment (UE), sidelink received signal strength indicator (SL-RSSI) values and sidelink reference signal power received (SL-RSRP) values from a current window of a communication channel shared among a plurality of UEs, excluding a first subset of communication resources from a next window of the communication channel based on the SL-RSSI values in the current window, excluding a second subset of communication resources from the next window of the communication channel based on the SL-RSRP values, and selecting and reserving a resource(s) remaining in the next window of the communication channel after exclusion of the first and second subsets of communication resources from the next window.

Abstract: One example embodiment provides one or more of: measuring, via a user equipment (UE), sidelink received signal strength indicator (SL-RSSI) values and sidelink reference signal power received (SL-RSRP) values from a current window of a communication channel shared among a plurality of UEs, measuring, via the UE, the SL-RSRP values from a frequency-domain and a time-domain of a current window of a communication channel shared among the plurality of UEs, excluding a first subset of communication resources from a next window of the communication channel based on the RSSI values in the current window, excluding a first subset of communication resources from a next window of the communication channel based on the SL-RSRP values from a time-domain, excluding a second subset of communication resources from the next window of the communication channel based on the RSRP values, excluding a second subset of communication resources from the next window of the communication channel based on the SL-RSRP values from a freq

Abstract: Embodiments of this application provide a next hop determining method. The method is applied to a BIER domain based on bit index forwarding routing, and includes: A third device obtains first BIER information of a first device, an attribute of the first device, second BIER information of a second device, and an attribute of the second device, where the first BIER information includes a bit forwarding router identifier BFR-id of an edge bit forwarding router BFR in a sub-domain, and the second BIER information includes the BFR-id of the edge BFR in the sub-domain. The third device determines, based on the first BIER information, the second BIER information, the attribute of the first device, and the attribute of the second device, a next hop to the edge BFR in the sub-domain.

Abstract: An electronic device and a performance optimization method thereof are provided. The electronic device includes a battery module, a processor, and a controller. The battery module is configured to supply power to the electronic device. The processor has a power limit. The controller is configured to monitor a charging and discharging current of the battery module. In a power connection mode, the controller analyzes a status of the battery module and adjusts the power limit of the processor according to the charging and discharging current.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The fin has a wide portion and a width-transition portion. The width-transition portion tapers away from the wide portion in a top view of the substrate, and a first top surface of the wide portion is higher than a second top surface of the width-transition portion. The semiconductor device structure includes a gate stack wrapped around the wide portion. The semiconductor device structure includes a dielectric dummy gate wrapped around the width-transition portion.

Abstract: A method of analyzing source code includes receiving, by a processor, an updated version of a computer program, the updated version including a source code. The method also includes preprocessing, by a compiler, the source code for a target computing platform. Preprocessing the source code by the compiler includes identifying a macro condition associated with one or more computer instructions enclosed by a macro, determining object code corresponding to the one or more computer instructions based on a current value of the macro condition, and generating object code and macro information for output to a debugger, the macro information including one or more breakpoint conditions in the macro.

Abstract: A method for predicting and controlling a water level of a series water conveyance canal on the basis of a fuzzy neural network is disclosed. The method includes: performing the relationship between a sluice opening degree and an open canal control water level by means of a fuzzy neural network, and constructing an upstream water level controller of a coupled predictive control algorithm; solving an optimal control rate of the upstream water level controller using a gradient optimization algorithm on the basis of a control target of the upstream water level controller; and generating a control strategy by collecting actually measured water level change information and multiplying the actually measured water level change information by the optimal control rate on the basis of the solved optimal control rate, thereby fulfilling the object of predicting and controlling the water level.

Abstract: A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes channel members over a backside dielectric feature, a gate structure wrapping around the channel members, an epitaxial feature abutting the channel members, a first isolation feature disposed on a first sidewall of the gate structure and extending through the backside dielectric feature, and a second isolation feature disposed on a second sidewall of the gate structure and extending through the backside dielectric feature. A top surface of the first isolation feature is above a top surface of the second isolation feature.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and multiple first conductive lines over the semiconductor substrate. The first conductive lines are not electrically connected to each other. The semiconductor device structure also includes multiple first magnetic structures wrapped around portions of the first conductive lines and multiple second conductive lines over the semiconductor substrate. The second conductive lines are electrically connected in series. The semiconductor device structure further includes multiple second magnetic structures wrapped around portions of the second conductive lines. A size of each of the second magnetic structures and a size of each of the first magnetic structures are substantially the same.

Abstract: An electrode for an electrochemical energy storage device formed from an electrostatic deposition process employs a composite particle including active material (AM) particle with adhered binder and optionally conductive particles formed with sufficient interaction forces between the individual ingredient particles to form an effective composite particle which can overcome particle separation during electrostatic charging, fluidization, and/or mechanical conveyance. Secondary binder particles undergo deagglomeration to form sub particles, which are adhered to the AM particles having a predetermined morphology. Smaller conductive particles, typically carbon black (CB) or similar carbon, are bound to the binder and adhere to the AM particles. The result is a composite particle adhered for withstanding separation forces imposed from electrostatic deposition onto a current collector.

Abstract: An electrode for an electrochemical energy storage device formed from an electrostatic deposition process employs a composite particle including active material (AM) particle with adhered binder and optionally conductive particles formed with sufficient interaction forces between the individual ingredient particles to form an effective composite particle which can overcome particle separation during electrostatic charging, fluidization, and/or mechanical conveyance. Secondary binder particles undergo deagglomeration to form sub particles, which are adhered to the AM particles having a predetermined morphology. Smaller conductive particles, typically carbon black (CB) or similar carbon, are bound to the binder and adhere to the AM particles. The result is a composite particle adhered for withstanding separation forces imposed from electrostatic deposition onto a current collector.

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.