Abstract: A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2. Wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other and wherein the substrate includes a tapered surface in the Y-direction.

Abstract: Reductants may reduce microbial bioburden in protein solutions. Reducing bioburden can increase shelf life or ensure the safety of food or pharmaceutical products. The use of reductants to reduce bioburden in producing non-animal-based food products may also have additional advantages. For example, chroma and hue angle may be improved so that the non-animal-based food products may closely resemble the appearance of animal-based food products. Embodiments may include a method for forming a food product precursor. The method may include providing a first mixture. The first mixture may include a protein. The method may further include adding a reductant to the first mixture to form a second mixture. The method may also include heating the second mixture at a temperature for a duration to form a third mixture. The third mixture may be the food product precursor. Embodiments may include the food product precursor.

Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Abstract: A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

Abstract: Embodiments of present invention provide a semiconductor device. The semiconductor device includes a silicon (Si) substrate containing a set of short channel field-effect-transistors (FETs); a germanium (Ge) layer on top of the Si substrate containing a set of long channel p-type FETs (PFETs); and an oxide semiconductor layer on top of the Ge layer containing a set of long channel n-type FETs (NFETs), wherein the set of short channel FETs, long channel PFETs, and long channel NFETs are interconnected through a set of far-back-end-of-line (FBEOL) layers.

Abstract: A stacked transistor structure including a top source drain region above a bottom source drain region, wherein a width of the bottom source drain region is greater than a width of the top source drain region, a bottom contact structure directly above and in electrical contact with the bottom source drain region, a replacement spacer surrounding the bottom contact structure, and a top gate spacer separating the replacement spacer from a gate conductor.

Abstract: According to one embodiment of the present invention, a computer-implemented method for dynamically altering a frequency at which data scrubbing is performed on a memory device is disclosed. The computer-implemented method includes monitoring at least one of a temperature and a magnetic field of the memory device. The computer-implemented method further includes, responsive to determining that at least one of the temperature and the magnetic field of the memory device reaches and/or exceeds a predetermined threshold, respectively, increasing the frequency at which data scrubbing is performed on the memory device.

Abstract: Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.

Abstract: A memory device includes a bit line structure disposed over a semiconductor substrate, and a lower capacitor contact disposed over the semiconductor substrate and adjacent to the bit line structure. The memory device also includes a first nitride spacer and a second nitride spacer disposed between the bit line structure and the lower capacitor contact. The memory device further includes a capacitor disposed over the first nitride spacer and the second nitride spacer. In addition, the memory device includes a first oxide liner and a second oxide liner disposed between the first nitride spacer and the second nitride spacer. An air gap is between the first oxide liner and the second oxide liner.

Abstract: A memory device includes a bit line structure disposed over a semiconductor substrate, and a lower capacitor contact disposed over the semiconductor substrate and adjacent to the bit line structure. The memory device also includes a first nitride spacer and a second nitride spacer disposed between the bit line structure and the lower capacitor contact. The memory device further includes a capacitor disposed over the first nitride spacer and the second nitride spacer. In addition, the memory device includes a first oxide liner and a second oxide liner disposed between the first nitride spacer and the second nitride spacer. An air gap is between the first oxide liner and the second oxide liner.

Abstract: A semiconductor device includes a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, a third nitride layer, and an electrode layer. The first nitride layer is disposed over the landing pad. The first oxide layer is disposed on the first nitride layer. The second nitride layer is disposed on the first oxide layer. The second oxide layer is disposed on the second nitride layer. The third nitride layer is disposed on the second oxide layer. A trench runs through the third nitride layer, the second oxide layer, the second nitride layer, the first oxide layer, and the first nitride layer. The trench further has an expanding portion through the first nitride layer. The electrode layer is disposed on an inner sidewall of the trench and a top surface of the third nitride layer.

Abstract: The present disclosure provides a semiconductor device, a semiconductor structure and a formation method thereof, and relates to the field of semiconductor technologies. The formation method includes: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer to form trenches and through holes distributed side by side in the sacrificial layer; forming insulating layers covering a sidewall of the trench and a sidewall of the through hole; sequentially forming a conductive layer and a passivation layer in the trench and the through hole to form a bitline structure in the trench; and removing the passivation layer in the through hole to form a capacitor contact structure in the through hole.

Abstract: A semiconductor device includes a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a third nitride layer, an electrode layer, and a filling material. The landing pad, the first nitride layer, the first oxide layer, the second nitride layer, and the third nitride layer are sequentially formed. A trench runs through the third nitride layer, the second oxide layer, the second nitride layer, the first oxide layer, and the first nitride layer. The electrode layer is disposed on an inner sidewall of the trench, a top surface of the third nitride layer, and a top surface and a sidewall of the landing pad. The filling material is filled in the trench and contacts the landing pad by the electrode layer.

Abstract: Disclosed herein are antibodies and compositions used for binding to Gal3. Some embodiments allow for disrupting interactions between Galectin-3 (Gal3) and cell surface markers and/or proteins associated with neurological diseases and/or proteopathies, such as Alzheimer's disease. Additionally, disclosed herein are methods of treatment and uses of the antibodies or binding fragments thereof for the treatment of fibrosis, liver fibrosis, kidney fibrosis, cardiac fibrosis, pulmonary fibrosis, non-alcoholic fatty liver disease, non-alcoholic steatohepatitis, sepsis, atopic dermatitis, psoriasis, cancer, brain cancer, breast cancer, colorectal cancer, kidney cancer, liver cancer, lung cancer, pancreatic cancer, bladder cancer, stomach cancer, hematological malignancy, neurological diseases and/or proteopathies. Furthermore, some embodiments provided herein can cross the blood-brain barrier and can be conjugated or otherwise associated with one or more payloads for the treatment of a neurological disease.

Abstract: A method includes a number of operations. An oxide layer is formed in an isolation trench over a substrate. A liner is formed over the oxide layer. The liner is oxidized. An implant region is formed over the substrate after the liner is oxidized. The oxide layer and the liner are etched after the implant region is formed. A word line structure is formed over the substrate and across the oxide layer and the liner.

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternately stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

Abstract: Embodiments are disclosed for a system that includes a data scrubbing circuit, a magnetoresistive random access memory (MRAM) having a memory array, and an analog persistent vital information circuit (APVIC) that performs a method. The method includes resetting weights corresponding to blocks of the memory array. The method further includes adjusting the weights based on a timer, data accesses on the memory blocks, and weight change values corresponding to the weights. The method also includes determining, in response to the timer, a data scrubbing threshold based on ambient temperature and magnetic field strength. The method additionally includes determining one of the weights meets the data scrubbing threshold. Further, the method includes providing, in response to the determination, an indication that a data scrubber, scrub one of the memory blocks corresponding to the weight that meets the data scrubbing threshold. Also, the method includes resetting the weight.

Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.

Abstract: The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.

Abstract: A switch short-circuited diagnosis method includes steps of: determining an initial voltage interval of multiple voltage intervals according to voltage relationships between voltages of a first phase wire, a second phase wire, and a third phase wire; performing a switch short-circuited diagnosis of a first bidirectional switch module in the three consecutive voltage intervals from the initial voltage interval, and including steps of: turning on a first switch branch, a second switch branch, or a third switch branch of the first bidirectional switch module according to the voltage relationships between the voltages of the first, second and third phase wires, determining whether an overcurrent occurs to diagnose whether the first switch branch, the second switch branch, or the third switch branch of the first bidirectional switch module is in a short-circuited state, and performing the switch short-circuited diagnosis for the next voltage interval.