Patents by Inventor Heng-Yi Chao
Heng-Yi Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10387604Abstract: Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. Specifically, some embodiments perform global routing using an iterative approach. During operation, the system determines bounding boxes for nets, and associates nets with partitions, wherein a partition associated with a net encloses the net's bounding box. Then, the system routes nets in non-overlapping partitions in parallel. Next, the system adjusts bounding boxes of nets which need to be routed again, and routes these nets in the next iteration. In some embodiments, the system may use a cost function to guide the routing process. The system may adjust the weights of one or more terms of the cost function as the routing process progresses. Specifically, the system may increase the importance of a congestion term as the routing process progresses.Type: GrantFiled: January 28, 2010Date of Patent: August 20, 2019Assignee: SYNOPSYS, INC.Inventors: Tong Gao, Heng-Yi Chao
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Publication number: 20110055784Abstract: Some embodiments provide techniques and systems for routing nets in a circuit design in parallel. Specifically, some embodiments perform global routing using an iterative approach. During operation, the system determines bounding boxes for nets, and associates nets with partitions, wherein a partition associated with a net encloses the net's bounding box. Then, the system routes nets in non-overlapping partitions in parallel. Next, the system adjusts bounding boxes of nets which need to be routed again, and routes these nets in the next iteration. In some embodiments, the system may use a cost function to guide the routing process. The system may adjust the weights of one or more terms of the cost function as the routing process progresses. Specifically, the system may increase the importance of a congestion term as the routing process progresses.Type: ApplicationFiled: January 28, 2010Publication date: March 3, 2011Applicant: SYNOPSYS, INC.Inventors: Tong Gao, Heng-Yi Chao
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Patent number: 7139994Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of an integrated circuit (“IC”) layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. For a particular set of potential sub-regions, the method then identifies a set of routes that traverse the particular set of potential sub-regions, where at least one of the identified routes has at least one diagonal edge. The method then stores the identified routes.Type: GrantFiled: January 7, 2002Date of Patent: November 21, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Joseph L. Ganley, Heng-Yi Chao
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Patent number: 7096448Abstract: Some embodiments provide a method of routing nets within a region of an integrated-circuit (“IC”) layout. The method uses a first set of lines to partition the IC region into a plurality of sub-regions. In addition, the method uses a second set of lines to measure congestion of routes for the nets within the IC region. According to this method, at least some of the lines in the second set are different from the lines in the first set.Type: GrantFiled: January 5, 2002Date of Patent: August 22, 2006Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Oscar Buset, Heng-Yi Chao
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Patent number: 6877149Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of a circuit layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. The method then identifies a primary set of sub-regions that has more than one sub-region. It then determines whether the primary set of sub-regions is an open set that has a sub-region that is not adjacent to any other sub-region in the set. If the primary set of sub-regions is not an open set, the method identifies a route that connects the sub-regions in the primary set, and stores the identified route for the primary set of sub-regions.Type: GrantFiled: January 13, 2002Date of Patent: April 5, 2005Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Heng-Yi Chao
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Patent number: 6618849Abstract: Some embodiments of the invention provide a method that identifies a set of routes for a net that has a set of pins in a region of a design layout. The method initially partitions the region into a number of sub-regions. It then identifies a first set of sub-regions that contains the net's pins. The method next determines whether a storage structure stores a set of routes for the identified first set of sub-regions. If so, the method retrieves the set of routes. If not, the method generates a set of routes. In some embodiments, the method generates a set of routes by first identifying a connection set of sub-regions that when combined with the first set forms a closed set of sub-regions. The closed set of sub-regions does not have any sub-region that is not adjacent to another sub-region in the closed set. The storage structure stores a set of routes for the closed set.Type: GrantFiled: January 13, 2002Date of Patent: September 9, 2003Assignee: Cadence Design Systems, Inc.Inventors: Steven Teig, Heng-Yi Chao
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Publication number: 20030101428Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.Type: ApplicationFiled: January 5, 2002Publication date: May 29, 2003Inventors: Steven Teig, Oscar Bust, Heng-Yi Chao
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Publication number: 20030088844Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.Type: ApplicationFiled: January 7, 2002Publication date: May 8, 2003Inventors: Steven Teig, Joseph L. Ganley, Heng-Yi Chao
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Publication number: 20030066045Abstract: Some embodiments of the invention provide a method that identifies a set of routes for a net that has a set of pins in a region of a design layout. The method initially partitions the region into a number of sub-regions. It then identifies a first set of sub-regions that contains the net's pins. The method next determines whether a storage structure stores a set of routes for the identified first set of sub-regions. If so, the method retrieves the set of routes. If not, the method generates a set of routes. In some embodiments, the method generates a set of routes by first identifying a connection set of sub-regions that when combined with the first set forms a closed set of sub-regions. The closed set of sub-regions does not have any sub-region that is not adjacent to another sub-region in the closed set. The storage structure stores a set of routes for the closed set. For the first set, the method then retrieves the set of routes that are stored for the closed set of sub-regions from the storage structure.Type: ApplicationFiled: January 13, 2002Publication date: April 3, 2003Inventors: Steven Teig, Heng-Yi Chao